drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
Extension
.h
Size
7370 bytes
Lines
238
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __RZG2L_MIPI_DSI_REGS_H__
#define __RZG2L_MIPI_DSI_REGS_H__

#include <linux/bits.h>

/* DPHY Registers */
#define DSIDPHYCTRL0			0x00
#define DSIDPHYCTRL0_CAL_EN_HSRX_OFS	BIT(16)
#define DSIDPHYCTRL0_CMN_MASTER_EN	BIT(8)
#define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18	BIT(2)
#define DSIDPHYCTRL0_EN_LDO1200		BIT(1)
#define DSIDPHYCTRL0_EN_BGR		BIT(0)

#define DSIDPHYTIM0			0x04
#define DSIDPHYTIM0_TCLK_MISS(x)	((x) << 24)
#define DSIDPHYTIM0_T_INIT(x)		((x) << 0)

#define DSIDPHYTIM1			0x08
#define DSIDPHYTIM1_THS_PREPARE(x)	((x) << 24)
#define DSIDPHYTIM1_TCLK_PREPARE(x)	((x) << 16)
#define DSIDPHYTIM1_THS_SETTLE(x)	((x) << 8)
#define DSIDPHYTIM1_TCLK_SETTLE(x)	((x) << 0)

#define DSIDPHYTIM2			0x0c
#define DSIDPHYTIM2_TCLK_TRAIL(x)	((x) << 24)
#define DSIDPHYTIM2_TCLK_POST(x)	((x) << 16)
#define DSIDPHYTIM2_TCLK_PRE(x)		((x) << 8)
#define DSIDPHYTIM2_TCLK_ZERO(x)	((x) << 0)

#define DSIDPHYTIM3			0x10
#define DSIDPHYTIM3_TLPX(x)		((x) << 24)
#define DSIDPHYTIM3_THS_EXIT(x)		((x) << 16)
#define DSIDPHYTIM3_THS_TRAIL(x)	((x) << 8)
#define DSIDPHYTIM3_THS_ZERO(x)		((x) << 0)

/* RZ/V2H DPHY Registers */
#define PLLENR				0x000
#define PLLENR_PLLEN			BIT(0)

#define PHYRSTR				0x004
#define PHYRSTR_PHYMRSTN		BIT(0)

#define PLLCLKSET0R			0x010
#define PLLCLKSET0R_PLL_S		GENMASK(2, 0)
#define PLLCLKSET0R_PLL_P		GENMASK(13, 8)
#define PLLCLKSET0R_PLL_M		GENMASK(25, 16)

#define PLLCLKSET1R			0x014
#define PLLCLKSET1R_PLL_K		GENMASK(15, 0)

#define PHYTCLKSETR			0x020
#define PHYTCLKSETR_TCLKTRAILCTL        GENMASK(7, 0)
#define PHYTCLKSETR_TCLKPOSTCTL         GENMASK(15, 8)
#define PHYTCLKSETR_TCLKZEROCTL         GENMASK(23, 16)
#define PHYTCLKSETR_TCLKPRPRCTL         GENMASK(31, 24)

#define PHYTHSSETR			0x024
#define PHYTHSSETR_THSEXITCTL           GENMASK(7, 0)
#define PHYTHSSETR_THSTRAILCTL          GENMASK(15, 8)
#define PHYTHSSETR_THSZEROCTL           GENMASK(23, 16)
#define PHYTHSSETR_THSPRPRCTL           GENMASK(31, 24)

#define PHYTLPXSETR			0x028
#define PHYTLPXSETR_TLPXCTL             GENMASK(7, 0)

#define PHYCR				0x030
#define PHYCR_ULPSEXIT                  GENMASK(9, 0)

/* --------------------------------------------------------*/

/* Link Status Register */
#define LINKSR				0x10
#define LINKSR_LPBUSY			BIT(13)
#define LINKSR_HSBUSY			BIT(12)
#define LINKSR_VICHRUN1			BIT(8)
#define LINKSR_SQCHRUN1			BIT(4)
#define LINKSR_SQCHRUN0			BIT(0)

/* Tx Set Register */
#define TXSETR				0x100
#define TXSETR_NUMLANECAP		(0x3 << 16)
#define TXSETR_DLEN			(1 << 9)
#define TXSETR_CLEN			(1 << 8)
#define TXSETR_NUMLANEUSE(x)		(((x) & 0x3) << 0)

/* HS Clock Set Register */
#define HSCLKSETR			0x104
#define HSCLKSETR_HSCLKMODE_CONT	(1 << 1)
#define HSCLKSETR_HSCLKMODE_NON_CONT	(0 << 1)
#define HSCLKSETR_HSCLKRUN_HS		(1 << 0)

Annotation

Implementation Notes