drivers/gpu/drm/renesas/shmobile/shmob_drm_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/renesas/shmobile/shmob_drm_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/renesas/shmobile/shmob_drm_regs.h
Extension
.h
Size
9050 bytes
Lines
311
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SHMOB_DRM_REGS_H__
#define __SHMOB_DRM_REGS_H__

#include <linux/io.h>
#include <linux/jiffies.h>

#include "shmob_drm_drv.h"

/* Register definitions */
#define LDDCKPAT1R		0x400
#define LDDCKPAT2R		0x404
#define LDDCKR			0x410
#define LDDCKR_ICKSEL_BUS	(0 << 16)
#define LDDCKR_ICKSEL_MIPI	(1 << 16)
#define LDDCKR_ICKSEL_HDMI	(2 << 16)
#define LDDCKR_ICKSEL_EXT	(3 << 16)
#define LDDCKR_ICKSEL_MASK	(7 << 16)
#define LDDCKR_MOSEL		(1 << 6)
#define LDDCKSTPR		0x414
#define LDDCKSTPR_DCKSTS	(1 << 16)
#define LDDCKSTPR_DCKSTP	(1 << 0)
#define LDMT1R			0x418
#define LDMT1R_VPOL		(1 << 28)
#define LDMT1R_HPOL		(1 << 27)
#define LDMT1R_DWPOL		(1 << 26)
#define LDMT1R_DIPOL		(1 << 25)
#define LDMT1R_DAPOL		(1 << 24)
#define LDMT1R_HSCNT		(1 << 17)
#define LDMT1R_DWCNT		(1 << 16)
#define LDMT1R_IFM		(1 << 12)
#define LDMT1R_MIFTYP_RGB8	(0x0 << 0)
#define LDMT1R_MIFTYP_RGB9	(0x4 << 0)
#define LDMT1R_MIFTYP_RGB12A	(0x5 << 0)
#define LDMT1R_MIFTYP_RGB12B	(0x6 << 0)
#define LDMT1R_MIFTYP_RGB16	(0x7 << 0)
#define LDMT1R_MIFTYP_RGB18	(0xa << 0)
#define LDMT1R_MIFTYP_RGB24	(0xb << 0)
#define LDMT1R_MIFTYP_YCBCR	(0xf << 0)
#define LDMT1R_MIFTYP_SYS8A	(0x0 << 0)
#define LDMT1R_MIFTYP_SYS8B	(0x1 << 0)
#define LDMT1R_MIFTYP_SYS8C	(0x2 << 0)
#define LDMT1R_MIFTYP_SYS8D	(0x3 << 0)
#define LDMT1R_MIFTYP_SYS9	(0x4 << 0)
#define LDMT1R_MIFTYP_SYS12	(0x5 << 0)
#define LDMT1R_MIFTYP_SYS16A	(0x7 << 0)
#define LDMT1R_MIFTYP_SYS16B	(0x8 << 0)
#define LDMT1R_MIFTYP_SYS16C	(0x9 << 0)
#define LDMT1R_MIFTYP_SYS18	(0xa << 0)
#define LDMT1R_MIFTYP_SYS24	(0xb << 0)
#define LDMT1R_MIFTYP_MASK	(0xf << 0)
#define LDMT2R			0x41c
#define LDMT2R_CSUP_MASK	(7 << 26)
#define LDMT2R_CSUP_SHIFT	26
#define LDMT2R_RSV		(1 << 25)
#define LDMT2R_VSEL		(1 << 24)
#define LDMT2R_WCSC_MASK	(0xff << 16)
#define LDMT2R_WCSC_SHIFT	16
#define LDMT2R_WCEC_MASK	(0xff << 8)
#define LDMT2R_WCEC_SHIFT	8
#define LDMT2R_WCLW_MASK	(0xff << 0)
#define LDMT2R_WCLW_SHIFT	0
#define LDMT3R			0x420
#define LDMT3R_RDLC_MASK	(0x3f << 24)
#define LDMT3R_RDLC_SHIFT	24
#define LDMT3R_RCSC_MASK	(0xff << 16)
#define LDMT3R_RCSC_SHIFT	16
#define LDMT3R_RCEC_MASK	(0xff << 8)
#define LDMT3R_RCEC_SHIFT	8
#define LDMT3R_RCLW_MASK	(0xff << 0)
#define LDMT3R_RCLW_SHIFT	0
#define LDDFR			0x424
#define LDDFR_CF1		(1 << 18)
#define LDDFR_CF0		(1 << 17)
#define LDDFR_CC		(1 << 16)
#define LDDFR_YF_420		(0 << 8)
#define LDDFR_YF_422		(1 << 8)
#define LDDFR_YF_444		(2 << 8)
#define LDDFR_YF_MASK		(3 << 8)
#define LDDFR_PKF_ARGB32	(0x00 << 0)
#define LDDFR_PKF_RGB16		(0x03 << 0)
#define LDDFR_PKF_RGB24		(0x0b << 0)
#define LDDFR_PKF_MASK		(0x1f << 0)
#define LDSM1R			0x428
#define LDSM1R_OS		(1 << 0)
#define LDSM2R			0x42c
#define LDSM2R_OSTRG		(1 << 0)
#define LDSA1R			0x430
#define LDSA2R			0x434
#define LDMLSR			0x438
#define LDWBFR			0x43c

Annotation

Implementation Notes