drivers/gpu/drm/rockchip/cdn-dp-core.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/rockchip/cdn-dp-core.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/rockchip/cdn-dp-core.c- Extension
.c- Size
- 27773 bytes
- Lines
- 1182
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/component.hlinux/extcon.hlinux/firmware.hlinux/mfd/syscon.hlinux/phy/phy.hlinux/regmap.hlinux/reset.hsound/hdmi-codec.hdrm/display/drm_dp_helper.hdrm/display/drm_hdmi_audio_helper.hdrm/drm_atomic_helper.hdrm/drm_bridge_connector.hdrm/drm_edid.hdrm/drm_of.hdrm/drm_print.hdrm/drm_probe_helper.hdrm/drm_simple_kms_helper.hcdn-dp-core.hcdn-dp-reg.h
Detected Declarations
struct cdn_dp_datafunction Copyrightfunction cdn_dp_grf_writefunction cdn_dp_clk_enablefunction cdn_dp_clk_disablefunction cdn_dp_get_port_lanesfunction cdn_dp_get_sink_countfunction cdn_dp_check_sink_connectionfunction cdn_dp_bridge_detectfunction cdn_dp_bridge_edid_readfunction cdn_dp_bridge_mode_validfunction cdn_dp_firmware_initfunction cdn_dp_get_sink_capabilityfunction cdn_dp_enable_phyfunction cdn_dp_disable_phyfunction cdn_dp_disablefunction cdn_dp_enablefunction cdn_dp_bridge_mode_setfunction cdn_dp_check_link_statusfunction cdn_dp_display_info_updatefunction cdn_dp_bridge_atomic_enablefunction cdn_dp_bridge_atomic_disablefunction cdn_dp_encoder_atomic_checkfunction cdn_dp_parse_dtfunction cdn_dp_audio_preparefunction cdn_dp_audio_shutdownfunction cdn_dp_audio_mute_streamfunction cdn_dp_request_firmwarefunction cdn_dp_pd_event_workfunction cdn_dp_pd_eventfunction cdn_dp_bindfunction cdn_dp_unbindfunction cdn_dp_suspendfunction cdn_dp_resumefunction cdn_dp_probefunction cdn_dp_removefunction cdn_dp_shutdown
Annotated Snippet
struct cdn_dp_data {
u8 max_phy;
};
static struct cdn_dp_data rk3399_cdn_dp = {
.max_phy = 2,
};
static const struct of_device_id cdn_dp_dt_ids[] = {
{ .compatible = "rockchip,rk3399-cdn-dp",
.data = (void *)&rk3399_cdn_dp },
{}
};
MODULE_DEVICE_TABLE(of, cdn_dp_dt_ids);
static int cdn_dp_grf_write(struct cdn_dp_device *dp,
unsigned int reg, unsigned int val)
{
int ret;
ret = clk_prepare_enable(dp->grf_clk);
if (ret) {
DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n");
return ret;
}
ret = regmap_write(dp->grf, reg, val);
if (ret) {
DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
clk_disable_unprepare(dp->grf_clk);
return ret;
}
clk_disable_unprepare(dp->grf_clk);
return 0;
}
static int cdn_dp_clk_enable(struct cdn_dp_device *dp)
{
int ret;
unsigned long rate;
ret = clk_prepare_enable(dp->pclk);
if (ret < 0) {
DRM_DEV_ERROR(dp->dev, "cannot enable dp pclk %d\n", ret);
goto err_pclk;
}
ret = clk_prepare_enable(dp->core_clk);
if (ret < 0) {
DRM_DEV_ERROR(dp->dev, "cannot enable core_clk %d\n", ret);
goto err_core_clk;
}
ret = pm_runtime_get_sync(dp->dev);
if (ret < 0) {
DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret);
goto err_pm_runtime_get;
}
reset_control_assert(dp->core_rst);
reset_control_assert(dp->dptx_rst);
reset_control_assert(dp->apb_rst);
reset_control_deassert(dp->core_rst);
reset_control_deassert(dp->dptx_rst);
reset_control_deassert(dp->apb_rst);
rate = clk_get_rate(dp->core_clk);
if (!rate) {
DRM_DEV_ERROR(dp->dev, "get clk rate failed\n");
ret = -EINVAL;
goto err_set_rate;
}
cdn_dp_set_fw_clk(dp, rate);
cdn_dp_clock_reset(dp);
return 0;
err_set_rate:
pm_runtime_put(dp->dev);
err_pm_runtime_get:
clk_disable_unprepare(dp->core_clk);
err_core_clk:
clk_disable_unprepare(dp->pclk);
err_pclk:
return ret;
}
Annotation
- Immediate include surface: `linux/clk.h`, `linux/component.h`, `linux/extcon.h`, `linux/firmware.h`, `linux/mfd/syscon.h`, `linux/phy/phy.h`, `linux/regmap.h`, `linux/reset.h`.
- Detected declarations: `struct cdn_dp_data`, `function Copyright`, `function cdn_dp_grf_write`, `function cdn_dp_clk_enable`, `function cdn_dp_clk_disable`, `function cdn_dp_get_port_lanes`, `function cdn_dp_get_sink_count`, `function cdn_dp_check_sink_connection`, `function cdn_dp_bridge_detect`, `function cdn_dp_bridge_edid_read`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.