drivers/gpu/drm/rockchip/rk3066_hdmi.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/rockchip/rk3066_hdmi.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/rockchip/rk3066_hdmi.h- Extension
.h- Size
- 6619 bytes
- Lines
- 230
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __RK3066_HDMI_H__
#define __RK3066_HDMI_H__
#define GRF_SOC_CON0 0x150
#define HDMI_VIDEO_SEL BIT(14)
#define DDC_SEGMENT_ADDR 0x30
#define HDMI_SCL_RATE (50 * 1000)
#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
#define N_32K 0x1000
#define N_441K 0x1880
#define N_882K 0x3100
#define N_1764K 0x6200
#define N_48K 0x1800
#define N_96K 0x3000
#define N_192K 0x6000
#define HDMI_SYS_CTRL 0x000
#define HDMI_LR_SWAP_N3 0x004
#define HDMI_N2 0x008
#define HDMI_N1 0x00c
#define HDMI_SPDIF_FS_CTS_INT3 0x010
#define HDMI_CTS_INT2 0x014
#define HDMI_CTS_INT1 0x018
#define HDMI_CTS_EXT3 0x01c
#define HDMI_CTS_EXT2 0x020
#define HDMI_CTS_EXT1 0x024
#define HDMI_AUDIO_CTRL1 0x028
#define HDMI_AUDIO_CTRL2 0x02c
#define HDMI_I2S_AUDIO_CTRL 0x030
#define HDMI_I2S_SWAP 0x040
#define HDMI_AUDIO_STA_BIT_CTRL1 0x044
#define HDMI_AUDIO_STA_BIT_CTRL2 0x048
#define HDMI_AUDIO_SRC_NUM_AND_LENGTH 0x050
#define HDMI_AV_CTRL1 0x054
#define HDMI_VIDEO_CTRL1 0x058
#define HDMI_DEEP_COLOR_MODE 0x05c
#define HDMI_EXT_VIDEO_PARA 0x0c0
#define HDMI_EXT_HTOTAL_L 0x0c4
#define HDMI_EXT_HTOTAL_H 0x0c8
#define HDMI_EXT_HBLANK_L 0x0cc
#define HDMI_EXT_HBLANK_H 0x0d0
#define HDMI_EXT_HDELAY_L 0x0d4
#define HDMI_EXT_HDELAY_H 0x0d8
#define HDMI_EXT_HDURATION_L 0x0dc
#define HDMI_EXT_HDURATION_H 0x0e0
#define HDMI_EXT_VTOTAL_L 0x0e4
#define HDMI_EXT_VTOTAL_H 0x0e8
#define HDMI_AV_CTRL2 0x0ec
#define HDMI_EXT_VBLANK_L 0x0f4
#define HDMI_EXT_VBLANK_H 0x10c
#define HDMI_EXT_VDELAY 0x0f8
#define HDMI_EXT_VDURATION 0x0fc
#define HDMI_CP_MANU_SEND_CTRL 0x100
#define HDMI_CP_AUTO_SEND_CTRL 0x104
#define HDMI_AUTO_CHECKSUM_OPT 0x108
#define HDMI_VIDEO_CTRL2 0x114
#define HDMI_PHY_OPTION 0x144
#define HDMI_CP_BUF_INDEX 0x17c
#define HDMI_CP_BUF_ACC_HB0 0x180
#define HDMI_CP_BUF_ACC_HB1 0x184
#define HDMI_CP_BUF_ACC_HB2 0x188
#define HDMI_CP_BUF_ACC_PB0 0x18c
#define HDMI_DDC_READ_FIFO_ADDR 0x200
#define HDMI_DDC_BUS_FREQ_L 0x204
#define HDMI_DDC_BUS_FREQ_H 0x208
#define HDMI_DDC_BUS_CTRL 0x2dc
#define HDMI_DDC_I2C_LEN 0x278
#define HDMI_DDC_I2C_OFFSET 0x280
#define HDMI_DDC_I2C_CTRL 0x284
#define HDMI_DDC_I2C_READ_BUF0 0x288
#define HDMI_DDC_I2C_READ_BUF1 0x28c
#define HDMI_DDC_I2C_READ_BUF2 0x290
#define HDMI_DDC_I2C_READ_BUF3 0x294
#define HDMI_DDC_I2C_WRITE_BUF0 0x298
#define HDMI_DDC_I2C_WRITE_BUF1 0x29c
#define HDMI_DDC_I2C_WRITE_BUF2 0x2a0
#define HDMI_DDC_I2C_WRITE_BUF3 0x2a4
#define HDMI_DDC_I2C_WRITE_BUF4 0x2ac
#define HDMI_DDC_I2C_WRITE_BUF5 0x2b0
#define HDMI_DDC_I2C_WRITE_BUF6 0x2b4
#define HDMI_INTR_MASK1 0x248
Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.