drivers/gpu/drm/stm/lvds.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/stm/lvds.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/stm/lvds.c
Extension
.c
Size
35943 bytes
Lines
1223
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct phy_reg_offsets {
	u32 GCR;	/* Global Control Register	*/
	u32 CMCR1;    /* Current Mode Control Register 1 */
	u32 CMCR2;    /* Current Mode Control Register 2 */
	u32 SCR;      /* Serial Control Register	*/
	u32 BCR1;     /* Bias Control Register 1	*/
	u32 BCR2;     /* Bias Control Register 2	*/
	u32 BCR3;     /* Bias Control Register 3	*/
	u32 MPLCR;    /* Monitor PLL Lock Control Register */
	u32 DCR;      /* Debug Control Register	*/
	u32 SSR1;     /* Spare Status Register 1	*/
	u32 CFGCR;    /* Configuration Control Register */
	u32 PLLCR1;   /* PLL_MODE 1 Control Register	*/
	u32 PLLCR2;   /* PLL_MODE 2 Control Register	*/
	u32 PLLSR;    /* PLL Status Register	*/
	u32 PLLSDCR1; /* PLL_SD_1 Control Register	*/
	u32 PLLSDCR2; /* PLL_SD_2 Control Register	*/
	u32 PLLTWGCR1;/* PLL_TWG_1 Control Register	*/
	u32 PLLTWGCR2;/* PLL_TWG_2 Control Register	*/
	u32 PLLCPCR;  /* PLL_CP Control Register	*/
	u32 PLLTESTCR;/* PLL_TEST Control Register	*/
};

struct lvds_phy_info {
	u32 base;
	struct phy_reg_offsets ofs;
};

static struct lvds_phy_info lvds_phy_16ff_primary = {
	.base = 0x1000,
	.ofs = {
		.GCR = 0x0,
		.CMCR1 = 0xC,
		.CMCR2 = 0x10,
		.SCR = 0x20,
		.BCR1 = 0x2C,
		.BCR2 = 0x30,
		.BCR3 = 0x34,
		.MPLCR = 0x64,
		.DCR = 0x84,
		.SSR1 = 0x88,
		.CFGCR = 0xA0,
		.PLLCR1 = 0xC0,
		.PLLCR2 = 0xC4,
		.PLLSR = 0xC8,
		.PLLSDCR1 = 0xCC,
		.PLLSDCR2 = 0xD0,
		.PLLTWGCR1 = 0xD4,
		.PLLTWGCR2 = 0xD8,
		.PLLCPCR = 0xE0,
		.PLLTESTCR = 0xE8,
	}
};

static struct lvds_phy_info lvds_phy_16ff_secondary = {
	.base = 0x1100,
	.ofs = {
		.GCR = 0x0,
		.CMCR1 = 0xC,
		.CMCR2 = 0x10,
		.SCR = 0x20,
		.BCR1 = 0x2C,
		.BCR2 = 0x30,
		.BCR3 = 0x34,
		.MPLCR = 0x64,
		.DCR = 0x84,
		.SSR1 = 0x88,
		.CFGCR = 0xA0,
		.PLLCR1 = 0xC0,
		.PLLCR2 = 0xC4,
		.PLLSR = 0xC8,
		.PLLSDCR1 = 0xCC,
		.PLLSDCR2 = 0xD0,
		.PLLTWGCR1 = 0xD4,
		.PLLTWGCR2 = 0xD8,
		.PLLCPCR = 0xE0,
		.PLLTESTCR = 0xE8,
	}
};

struct stm_lvds {
	void __iomem *base;
	struct device *dev;
	struct clk *pclk;		/* APB peripheral clock */
	struct clk *pllref_clk;		/* Reference clock for the internal PLL */
	struct clk_hw lvds_ck_px;	/* Pixel clock */
	u32 pixel_clock_rate;		/* Pixel clock rate */

	struct lvds_phy_info *primary;
	struct lvds_phy_info *secondary;

Annotation

Implementation Notes