drivers/gpu/drm/tegra/gr3d.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/tegra/gr3d.h

Extension

.h

Size

686 bytes

Lines

25

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef TEGRA_GR3D_H
#define TEGRA_GR3D_H

#define GR3D_IDX_ATTRIBUTE(x)		(0x100 + (x) * 2)
#define GR3D_IDX_INDEX_BASE		0x121
#define GR3D_QR_ZTAG_ADDR		0x415
#define GR3D_QR_CTAG_ADDR		0x417
#define GR3D_QR_CZ_ADDR			0x419
#define GR3D_TEX_TEX_ADDR(x)		(0x710 + (x))
#define GR3D_DW_MEMORY_OUTPUT_ADDRESS	0x904
#define GR3D_GLOBAL_SURFADDR(x)		(0xe00 + (x))
#define GR3D_GLOBAL_SPILLSURFADDR	0xe2a
#define GR3D_GLOBAL_SURFOVERADDR(x)	(0xe30 + (x))
#define GR3D_GLOBAL_SAMP01SURFADDR(x)	(0xe50 + (x))
#define GR3D_GLOBAL_SAMP23SURFADDR(x)	(0xe60 + (x))

#define GR3D_NUM_REGS			0xe88

#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.