drivers/gpu/drm/tegra/hdmi.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/tegra/hdmi.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/tegra/hdmi.h- Extension
.h- Size
- 21959 bytes
- Lines
- 558
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef TEGRA_HDMI_H
#define TEGRA_HDMI_H 1
/* register definitions */
#define HDMI_CTXSW 0x00
#define HDMI_NV_PDISP_SOR_STATE0 0x01
#define SOR_STATE_UPDATE (1 << 0)
#define HDMI_NV_PDISP_SOR_STATE1 0x02
#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
#define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
#define SOR_STATE_ATTACHED (1 << 3)
#define HDMI_NV_PDISP_SOR_STATE2 0x03
#define SOR_STATE_ASY_OWNER_NONE (0 << 0)
#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
#define SOR_STATE_ASY_DEPOL_POS (0 << 14)
#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
#define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
#define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
#define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
#define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
#define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
#define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
#define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
#define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
#define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
#define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
#define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
#define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
#define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
#define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
#define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
#define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
#define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
#define HDMI_NV_PDISP_RG_HDCP_RI 0x17
#define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
#define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
#define INFOFRAME_CTRL_ENABLE (1 << 0)
#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
#define GENERIC_CTRL_ENABLE (1 << 0)
#define GENERIC_CTRL_OTHER (1 << 4)
#define GENERIC_CTRL_SINGLE (1 << 8)
#define GENERIC_CTRL_HBLANK (1 << 12)
#define GENERIC_CTRL_AUDIO (1 << 16)
#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.