drivers/gpu/drm/tegra/sor.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/tegra/sor.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/tegra/sor.h
Extension
.h
Size
16680 bytes
Lines
458
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef DRM_TEGRA_SOR_H
#define DRM_TEGRA_SOR_H

#define SOR_CTXSW 0x00

#define SOR_SUPER_STATE0 0x01

#define SOR_SUPER_STATE1 0x02
#define  SOR_SUPER_STATE_ATTACHED		(1 << 3)
#define  SOR_SUPER_STATE_MODE_NORMAL		(1 << 2)
#define  SOR_SUPER_STATE_HEAD_MODE_MASK		(3 << 0)
#define  SOR_SUPER_STATE_HEAD_MODE_AWAKE	(2 << 0)
#define  SOR_SUPER_STATE_HEAD_MODE_SNOOZE	(1 << 0)
#define  SOR_SUPER_STATE_HEAD_MODE_SLEEP	(0 << 0)

#define SOR_STATE0 0x03

#define SOR_STATE1 0x04
#define  SOR_STATE_ASY_PIXELDEPTH_MASK		(0xf << 17)
#define  SOR_STATE_ASY_PIXELDEPTH_BPP_18_444	(0x2 << 17)
#define  SOR_STATE_ASY_PIXELDEPTH_BPP_24_444	(0x5 << 17)
#define  SOR_STATE_ASY_PIXELDEPTH_BPP_30_444	(0x6 << 17)
#define  SOR_STATE_ASY_PIXELDEPTH_BPP_36_444	(0x8 << 17)
#define  SOR_STATE_ASY_PIXELDEPTH_BPP_48_444	(0x9 << 17)
#define  SOR_STATE_ASY_VSYNCPOL			(1 << 13)
#define  SOR_STATE_ASY_HSYNCPOL			(1 << 12)
#define  SOR_STATE_ASY_PROTOCOL_MASK		(0xf << 8)
#define  SOR_STATE_ASY_PROTOCOL_CUSTOM		(0xf << 8)
#define  SOR_STATE_ASY_PROTOCOL_DP_A		(0x8 << 8)
#define  SOR_STATE_ASY_PROTOCOL_DP_B		(0x9 << 8)
#define  SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A	(0x1 << 8)
#define  SOR_STATE_ASY_PROTOCOL_LVDS		(0x0 << 8)
#define  SOR_STATE_ASY_CRC_MODE_MASK		(0x3 << 6)
#define  SOR_STATE_ASY_CRC_MODE_NON_ACTIVE	(0x2 << 6)
#define  SOR_STATE_ASY_CRC_MODE_COMPLETE	(0x1 << 6)
#define  SOR_STATE_ASY_CRC_MODE_ACTIVE		(0x0 << 6)
#define  SOR_STATE_ASY_SUBOWNER_MASK		(0x3 << 4)
#define  SOR_STATE_ASY_OWNER_MASK		0xf
#define  SOR_STATE_ASY_OWNER(x)			(((x) & 0xf) << 0)

#define SOR_HEAD_STATE0(x) (0x05 + (x))
#define  SOR_HEAD_STATE_RANGECOMPRESS_MASK (0x1 << 3)
#define  SOR_HEAD_STATE_DYNRANGE_MASK (0x1 << 2)
#define  SOR_HEAD_STATE_DYNRANGE_VESA (0 << 2)
#define  SOR_HEAD_STATE_DYNRANGE_CEA (1 << 2)
#define  SOR_HEAD_STATE_COLORSPACE_MASK (0x3 << 0)
#define  SOR_HEAD_STATE_COLORSPACE_RGB (0 << 0)
#define SOR_HEAD_STATE1(x) (0x07 + (x))
#define SOR_HEAD_STATE2(x) (0x09 + (x))
#define SOR_HEAD_STATE3(x) (0x0b + (x))
#define SOR_HEAD_STATE4(x) (0x0d + (x))
#define SOR_HEAD_STATE5(x) (0x0f + (x))
#define SOR_CRC_CNTRL 0x11
#define  SOR_CRC_CNTRL_ENABLE			(1 << 0)
#define SOR_DP_DEBUG_MVID 0x12

#define SOR_CLK_CNTRL 0x13
#define  SOR_CLK_CNTRL_DP_LINK_SPEED_MASK	(0x1f << 2)
#define  SOR_CLK_CNTRL_DP_LINK_SPEED(x)		(((x) & 0x1f) << 2)
#define  SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62	(0x06 << 2)
#define  SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70	(0x0a << 2)
#define  SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40	(0x14 << 2)
#define  SOR_CLK_CNTRL_DP_CLK_SEL_MASK		(3 << 0)
#define  SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK	(0 << 0)
#define  SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK	(1 << 0)
#define  SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK	(2 << 0)
#define  SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK	(3 << 0)

#define SOR_CAP 0x14

#define SOR_PWR 0x15
#define  SOR_PWR_TRIGGER			(1 << 31)
#define  SOR_PWR_MODE_SAFE			(1 << 28)
#define  SOR_PWR_NORMAL_STATE_PU		(1 << 0)

#define SOR_TEST 0x16
#define  SOR_TEST_CRC_POST_SERIALIZE		(1 << 23)
#define  SOR_TEST_ATTACHED			(1 << 10)
#define  SOR_TEST_HEAD_MODE_MASK		(3 << 8)
#define  SOR_TEST_HEAD_MODE_AWAKE		(2 << 8)

#define SOR_PLL0 0x17
#define  SOR_PLL0_ICHPMP_MASK			(0xf << 24)
#define  SOR_PLL0_ICHPMP(x)			(((x) & 0xf) << 24)
#define  SOR_PLL0_FILTER_MASK			(0xf << 16)
#define  SOR_PLL0_FILTER(x)			(((x) & 0xf) << 16)
#define  SOR_PLL0_VCOCAP_MASK			(0xf << 8)
#define  SOR_PLL0_VCOCAP(x)			(((x) & 0xf) << 8)
#define  SOR_PLL0_VCOCAP_RST			SOR_PLL0_VCOCAP(3)
#define  SOR_PLL0_PLLREG_MASK			(0x3 << 6)

Annotation

Implementation Notes