drivers/gpu/drm/tidss/tidss_dispc.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/tidss/tidss_dispc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/tidss/tidss_dispc.c- Extension
.c- Size
- 80942 bytes
- Lines
- 3075
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/clk.hlinux/delay.hlinux/dma-mapping.hlinux/err.hlinux/interrupt.hlinux/io.hlinux/kernel.hlinux/media-bus-format.hlinux/module.hlinux/mfd/syscon.hlinux/of.hlinux/platform_device.hlinux/pm_runtime.hlinux/regmap.hlinux/sys_soc.hdrm/drm_blend.hdrm/drm_fourcc.hdrm/drm_fb_dma_helper.hdrm/drm_framebuffer.hdrm/drm_gem_dma_helper.hdrm/drm_panel.hdrm/drm_print.htidss_crtc.htidss_dispc.htidss_drv.htidss_irq.htidss_plane.htidss_dispc_regs.htidss_scale_coefs.h
Detected Declarations
struct dss_vp_datastruct dispc_devicestruct dispc_bus_formatstruct dispc_csc_coefstruct dispc_scaling_paramsenum c8_to_c12_modeenum csc_ctmenum csc_yuv2rgbenum csc_rgb2yuvenum dispc_vid_fir_coef_setfunction dispc_writefunction dispc_readfunction dispc_vid_writefunction dispc_vid_readfunction dispc_ovr_writefunction dispc_ovr_readfunction dispc_vp_writefunction dispc_vp_readfunction tidss_configure_oldifunction tidss_disable_oldifunction dispc_vp_irq_from_rawfunction dispc_vp_irq_to_rawfunction dispc_vid_irq_from_rawfunction dispc_vid_irq_to_rawfunction dispc_k2g_vp_read_irqstatusfunction dispc_k2g_vp_write_irqstatusfunction dispc_k2g_vid_read_irqstatusfunction dispc_k2g_vid_write_irqstatusfunction dispc_k2g_vp_read_irqenablefunction dispc_k2g_vp_set_irqenablefunction dispc_k2g_vid_read_irqenablefunction dispc_k2g_vid_set_irqenablefunction dispc_k2g_clear_irqstatusfunction dispc_k2g_read_and_clear_irqstatusfunction dispc_k2g_read_irqenablefunction dispc_k2g_set_irqenablefunction dispc_k3_vp_read_irqstatusfunction dispc_k3_vp_write_irqstatusfunction dispc_k3_vid_read_irqstatusfunction dispc_k3_vid_write_irqstatusfunction dispc_k3_vp_read_irqenablefunction dispc_k3_vp_set_irqenablefunction dispc_k3_vid_read_irqenablefunction dispc_k3_vid_set_irqenablefunction dispc_k3_clear_irqstatusfunction dispc_k3_read_and_clear_irqstatusfunction dispc_k3_read_irqenablefunction dispc_k3_set_irqenable
Annotated Snippet
struct dss_vp_data {
u32 *gamma_table;
};
struct dispc_device {
struct tidss_device *tidss;
struct device *dev;
void __iomem *base_common;
void __iomem *base_vid[TIDSS_MAX_PLANES];
void __iomem *base_ovr[TIDSS_MAX_PORTS];
void __iomem *base_vp[TIDSS_MAX_PORTS];
struct regmap *am65x_oldi_io_ctrl;
struct clk *vp_clk[TIDSS_MAX_PORTS];
const struct dispc_features *feat;
struct clk *fclk;
bool is_enabled;
struct dss_vp_data vp_data[TIDSS_MAX_PORTS];
u32 *fourccs;
u32 num_fourccs;
u32 memory_bandwidth_limit;
struct dispc_errata errata;
};
static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val)
{
iowrite32(val, dispc->base_common + reg);
}
static u32 dispc_read(struct dispc_device *dispc, u16 reg)
{
return ioread32(dispc->base_common + reg);
}
static
void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
{
void __iomem *base = dispc->base_vid[hw_plane];
iowrite32(val, base + reg);
}
static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)
{
void __iomem *base = dispc->base_vid[hw_plane];
return ioread32(base + reg);
}
static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport,
u16 reg, u32 val)
{
void __iomem *base = dispc->base_ovr[hw_videoport];
iowrite32(val, base + reg);
}
static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
{
void __iomem *base = dispc->base_ovr[hw_videoport];
return ioread32(base + reg);
}
static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport,
u16 reg, u32 val)
{
void __iomem *base = dispc->base_vp[hw_videoport];
iowrite32(val, base + reg);
}
static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
{
void __iomem *base = dispc->base_vp[hw_videoport];
return ioread32(base + reg);
}
int tidss_configure_oldi(struct tidss_device *tidss, u32 hw_videoport,
u32 oldi_cfg)
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/clk.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/err.h`, `linux/interrupt.h`, `linux/io.h`, `linux/kernel.h`.
- Detected declarations: `struct dss_vp_data`, `struct dispc_device`, `struct dispc_bus_format`, `struct dispc_csc_coef`, `struct dispc_scaling_params`, `enum c8_to_c12_mode`, `enum csc_ctm`, `enum csc_yuv2rgb`, `enum csc_rgb2yuv`, `enum dispc_vid_fir_coef_set`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.