drivers/gpu/drm/tidss/tidss_dispc_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/tidss/tidss_dispc_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/tidss/tidss_dispc_regs.h
Extension
.h
Size
12242 bytes
Lines
337
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __TIDSS_DISPC_REGS_H
#define __TIDSS_DISPC_REGS_H

enum dispc_common_regs {
	NOT_APPLICABLE_OFF = 0,
	DSS_REVISION_OFF,
	DSS_SYSCONFIG_OFF,
	DSS_SYSSTATUS_OFF,
	DISPC_IRQ_EOI_OFF,
	DISPC_IRQSTATUS_RAW_OFF,
	DISPC_IRQSTATUS_OFF,
	DISPC_IRQENABLE_SET_OFF,
	DISPC_IRQENABLE_CLR_OFF,
	DISPC_VID_IRQENABLE_OFF,
	DISPC_VID_IRQSTATUS_OFF,
	DISPC_VP_IRQENABLE_OFF,
	DISPC_VP_IRQSTATUS_OFF,
	WB_IRQENABLE_OFF,
	WB_IRQSTATUS_OFF,
	DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF,
	DISPC_GLOBAL_OUTPUT_ENABLE_OFF,
	DISPC_GLOBAL_BUFFER_OFF,
	DSS_CBA_CFG_OFF,
	DISPC_DBG_CONTROL_OFF,
	DISPC_DBG_STATUS_OFF,
	DISPC_CLKGATING_DISABLE_OFF,
	DISPC_SECURE_DISABLE_OFF,
	FBDC_REVISION_1_OFF,
	FBDC_REVISION_2_OFF,
	FBDC_REVISION_3_OFF,
	FBDC_REVISION_4_OFF,
	FBDC_REVISION_5_OFF,
	FBDC_REVISION_6_OFF,
	FBDC_COMMON_CONTROL_OFF,
	FBDC_CONSTANT_COLOR_0_OFF,
	FBDC_CONSTANT_COLOR_1_OFF,
	DISPC_CONNECTIONS_OFF,
	DISPC_MSS_VP1_OFF,
	DISPC_MSS_VP3_OFF,
	DISPC_COMMON_REG_TABLE_LEN,
};

/*
 * dispc_common_regmap should be defined as const u16 * and pointing
 * to a valid dss common register map for the platform, before the
 * macros below can be used.
 */

#define REG(r) (dispc_common_regmap[r ## _OFF])

#define DSS_REVISION			REG(DSS_REVISION)
#define DSS_SYSCONFIG			REG(DSS_SYSCONFIG)
#define DSS_SYSCONFIG_SOFTRESET_MASK		GENMASK(1, 1)

#define DSS_SYSSTATUS			REG(DSS_SYSSTATUS)
#define DSS_SYSSTATUS_DISPC_IDLE_STATUS		GENMASK(9, 9)
#define DSS_SYSSTATUS_DISPC_FUNC_RESETDONE	GENMASK(0, 0)

#define DISPC_IRQ_EOI			REG(DISPC_IRQ_EOI)
#define DISPC_IRQSTATUS_RAW		REG(DISPC_IRQSTATUS_RAW)
#define DISPC_IRQSTATUS			REG(DISPC_IRQSTATUS)
#define DISPC_IRQENABLE_SET		REG(DISPC_IRQENABLE_SET)
#define DISPC_IRQENABLE_CLR		REG(DISPC_IRQENABLE_CLR)
#define DISPC_VID_IRQENABLE(n)		(REG(DISPC_VID_IRQENABLE) + (n) * 4)
#define DISPC_VID_IRQSTATUS(n)		(REG(DISPC_VID_IRQSTATUS) + (n) * 4)
#define DISPC_VP_IRQENABLE(n)		(REG(DISPC_VP_IRQENABLE) + (n) * 4)
#define DISPC_VP_IRQSTATUS(n)		(REG(DISPC_VP_IRQSTATUS) + (n) * 4)
#define WB_IRQENABLE			REG(WB_IRQENABLE)
#define WB_IRQSTATUS			REG(WB_IRQSTATUS)

#define DISPC_GLOBAL_MFLAG_ATTRIBUTE	REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE)
#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK	GENMASK(6, 6)
#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK	GENMASK(1, 0)

#define DISPC_GLOBAL_OUTPUT_ENABLE	REG(DISPC_GLOBAL_OUTPUT_ENABLE)
#define DISPC_GLOBAL_BUFFER		REG(DISPC_GLOBAL_BUFFER)
#define DSS_CBA_CFG			REG(DSS_CBA_CFG)
#define DSS_CBA_CFG_PRI_HI_MASK			GENMASK(5, 3)
#define DSS_CBA_CFG_PRI_LO_MASK			GENMASK(2, 0)

#define DISPC_DBG_CONTROL		REG(DISPC_DBG_CONTROL)
#define DISPC_DBG_STATUS		REG(DISPC_DBG_STATUS)
#define DISPC_CLKGATING_DISABLE		REG(DISPC_CLKGATING_DISABLE)
#define DISPC_SECURE_DISABLE		REG(DISPC_SECURE_DISABLE)

#define FBDC_REVISION_1			REG(FBDC_REVISION_1)
#define FBDC_REVISION_2			REG(FBDC_REVISION_2)
#define FBDC_REVISION_3			REG(FBDC_REVISION_3)
#define FBDC_REVISION_4			REG(FBDC_REVISION_4)
#define FBDC_REVISION_5			REG(FBDC_REVISION_5)

Annotation

Implementation Notes