drivers/gpu/drm/tilcdc/tilcdc_drv.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/tilcdc/tilcdc_drv.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/tilcdc/tilcdc_drv.c
Extension
.c
Size
12655 bytes
Lines
503
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (0 == strcmp(str, "crossed")) {
			DBG("Configured for crossed blue and red wires");
			priv->pixelformats = tilcdc_crossed_formats;
			priv->num_pixelformats =
				ARRAY_SIZE(tilcdc_crossed_formats);
			bpp = 32; /* Choose bpp with RGB support for fbdef */
		} else if (0 == strcmp(str, "straight")) {
			DBG("Configured for straight blue and red wires");
			priv->pixelformats = tilcdc_straight_formats;
			priv->num_pixelformats =
				ARRAY_SIZE(tilcdc_straight_formats);
			bpp = 16; /* Choose bpp with RGB support for fbdef */
		} else {
			DBG("Blue and red wiring '%s' unknown, use legacy mode",
			    str);
			priv->pixelformats = tilcdc_legacy_formats;
			priv->num_pixelformats =
				ARRAY_SIZE(tilcdc_legacy_formats);
			bpp = 16; /* This is just a guess */
		}
	}

	if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
		priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;

	DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);

	if (of_property_read_u32(node, "max-width", &priv->max_width)) {
		if (priv->rev == 1)
			priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V1;
		else
			priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V2;
	}

	DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);

	if (of_property_read_u32(node, "max-pixelclock",
				 &priv->max_pixelclock))
		priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;

	DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);

	if (variant == DA850_TILCDC)
		priv->fifo_th = 16;
	else
		priv->fifo_th = 8;

	ret = tilcdc_crtc_create(ddev);
	if (ret < 0) {
		drm_err(ddev, "failed to create crtc\n");
		goto disable_pm;
	}
	modeset_init(ddev);

#ifdef CONFIG_CPU_FREQ
	priv->freq_transition.notifier_call = cpufreq_transition;
	ret = cpufreq_register_notifier(&priv->freq_transition,
			CPUFREQ_TRANSITION_NOTIFIER);
	if (ret) {
		drm_err(ddev, "failed to register cpufreq notifier\n");
		priv->freq_transition.notifier_call = NULL;
		goto disable_pm;
	}
#endif

	ret = tilcdc_encoder_create(ddev);
	if (ret)
		goto unregister_cpufreq_notif;

	if (!priv->connector) {
		drm_err(ddev, "no encoders/connectors found\n");
		ret = -EPROBE_DEFER;
		goto unregister_cpufreq_notif;
	}

	ret = drm_vblank_init(ddev, 1);
	if (ret < 0) {
		drm_err(ddev, "failed to initialize vblank\n");
		goto unregister_cpufreq_notif;
	}

	ret = platform_get_irq(pdev, 0);
	if (ret < 0)
		goto unregister_cpufreq_notif;
	priv->irq = ret;

	ret = tilcdc_irq_install(ddev, priv->irq);
	if (ret < 0) {
		drm_err(ddev, "failed to install IRQ handler\n");
		goto unregister_cpufreq_notif;

Annotation

Implementation Notes