drivers/gpu/drm/tyr/regs.rs

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/tyr/regs.rs

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/tyr/regs.rs
Extension
.rs
Size
58937 bytes
Lines
1657
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0 or MIT

//! # Definitions
//!
//! - **CEU**: Command Execution Unit - A hardware component that executes commands (instructions)
//!   from the command stream.
//! - **CS**: Command Stream - A sequence of instructions (commands) used to control a particular
//!   job or sequence of jobs. The instructions exist in one or more command buffers.
//! - **CSF**: Command Stream Frontend - The interface and implementation for job submission
//!   exposed to the host CPU driver. This includes the global interface, as well as CSG and CS
//!   interfaces.
//! - **CSG**: Command Stream Group - A group of related command streams. The CSF manages multiple
//!   CSGs, and each CSG contains multiple CSs.
//! - **CSHW**: Command Stream Hardware - The hardware interpreting command streams, including the
//!   iterator control aspects. Implements the CSF in conjunction with the MCU.
//! - **GLB**: Global - Prefix for global interface registers that control operations common to
//!   all CSs.
//! - **JASID**: Job Address Space ID - Identifies the address space for a job.
//! - **MCU**: Microcontroller Unit - Implements the CSF in conjunction with the command stream
//!   hardware.
//! - **MMU**: Memory Management Unit - Handles address translation and memory access protection.

// We don't expect that all the registers and fields will be used, even in the
// future.
//
// Nevertheless, it is useful to have most of them defined, like the C driver
// does.
#![allow(dead_code)]

/// Combine two 32-bit values into a single 64-bit value.
pub(crate) fn join_u64(lo: u32, hi: u32) -> u64 {
    (u64::from(lo)) | ((u64::from(hi)) << 32)
}

/// Read a logical 64-bit value from split 32-bit registers without tearing.
pub(crate) fn read_u64_no_tearing(lo_read: impl Fn() -> u32, hi_read: impl Fn() -> u32) -> u64 {
    loop {
        let hi1 = hi_read();
        let lo = lo_read();
        let hi2 = hi_read();

        if hi1 == hi2 {
            return join_u64(lo, hi1);
        }
    }
}

/// These registers correspond to the GPU_CONTROL register page.
/// They are involved in GPU configuration and control.
pub(crate) mod gpu_control {
    use core::convert::TryFrom;
    use kernel::{
        error::{
            code::EINVAL,
            Error, //
        },
        num::Bounded,
        register,
        uapi, //
    };
    use pin_init::Zeroable;

    register! {
        /// GPU identification register.
        pub(crate) GPU_ID(u32) @ 0x0 {
            /// Status of the GPU release.
            3:0     ver_status;
            /// Minor release version number.
            11:4    ver_minor;
            /// Major release version number.
            15:12   ver_major;
            /// Product identifier.
            19:16   prod_major;
            /// Architecture patch revision.
            23:20   arch_rev;
            /// Architecture minor revision.
            27:24   arch_minor;
            /// Architecture major revision.
            31:28   arch_major;
        }

        /// Level 2 cache features register.
        pub(crate) L2_FEATURES(u32) @ 0x4 {
            /// Cache line size.
            7:0     line_size;
            /// Cache associativity.
            15:8    associativity;
            /// Cache slice size.
            23:16   cache_size;
            /// External bus width.

Annotation

Implementation Notes