drivers/gpu/drm/vc4/vc4_dsi.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/vc4/vc4_dsi.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/vc4/vc4_dsi.c
Extension
.c
Size
55089 bytes
Lines
1827
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct vc4_dsi_variant {
	/* Whether we're on bcm2835's DSI0 or DSI1. */
	unsigned int port;

	bool broken_axi_workaround;

	const char *debugfs_name;
	const struct debugfs_reg32 *regs;
	size_t nregs;

};

/* General DSI hardware state. */
struct vc4_dsi {
	struct vc4_encoder encoder;
	struct mipi_dsi_host dsi_host;

	struct platform_device *pdev;

	struct drm_bridge *out_bridge;
	struct drm_bridge bridge;

	void __iomem *regs;

	struct dma_chan *reg_dma_chan;
	dma_addr_t reg_dma_paddr;
	u32 *reg_dma_mem;
	dma_addr_t reg_paddr;

	const struct vc4_dsi_variant *variant;

	/* DSI channel for the panel we're connected to. */
	u32 channel;
	u32 lanes;
	u32 format;
	u32 divider;
	u32 mode_flags;

	/* Input clock from CPRMAN to the digital PHY, for the DSI
	 * escape clock.
	 */
	struct clk *escape_clock;

	/* Input clock to the analog PHY, used to generate the DSI bit
	 * clock.
	 */
	struct clk *pll_phy_clock;

	/* HS Clocks generated within the DSI analog PHY. */
	struct clk_fixed_factor phy_clocks[3];

	struct clk_hw_onecell_data *clk_onecell;

	/* Pixel clock output to the pixelvalve, generated from the HS
	 * clock.
	 */
	struct clk *pixel_clock;

	struct completion xfer_completion;
	int xfer_result;

	struct debugfs_regset32 regset;
};

#define host_to_dsi(host)					\
	container_of_const(host, struct vc4_dsi, dsi_host)

#define to_vc4_dsi(_encoder)					\
	container_of_const(_encoder, struct vc4_dsi, encoder.base)

#define bridge_to_vc4_dsi(_bridge)				\
	container_of_const(_bridge, struct vc4_dsi, bridge)

static inline void
dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
{
	struct drm_device *drm = dsi->bridge.dev;
	struct dma_chan *chan = dsi->reg_dma_chan;
	struct dma_async_tx_descriptor *tx;
	dma_cookie_t cookie;
	int ret;

	kunit_fail_current_test("Accessing a register in a unit test!\n");

	/* DSI0 should be able to write normally. */
	if (!chan) {
		writel(val, dsi->regs + offset);
		return;
	}

Annotation

Implementation Notes