drivers/gpu/drm/vc4/vc4_hdmi_regs.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/vc4/vc4_hdmi_regs.h- Extension
.h- Size
- 22842 bytes
- Lines
- 729
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pm_runtime.hvc4_hdmi.h
Detected Declarations
struct vc4_hdmi_registerenum vc4_hdmi_regsenum vc4_hdmi_fieldfunction vc4_hdmi_readfunction vc4_hdmi_write
Annotated Snippet
struct vc4_hdmi_register {
char *name;
enum vc4_hdmi_regs reg;
unsigned int offset;
};
#define _VC4_REG(_base, _reg, _offset) \
[_reg] = { \
.name = #_reg, \
.reg = _base, \
.offset = _offset, \
}
#define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset)
#define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset)
#define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
#define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
#define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
#define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
#define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
#define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
VC4_HD_REG(HDMI_M_CTL, 0x000c),
VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
VC4_HD_REG(HDMI_MAI_THR, 0x0018),
VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
VC4_HD_REG(HDMI_VID_CTL, 0x0038),
VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x00e4),
VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
};
static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
VC4_HD_REG(HDMI_MAI_THR, 0x0014),
VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
Annotation
- Immediate include surface: `linux/pm_runtime.h`, `vc4_hdmi.h`.
- Detected declarations: `struct vc4_hdmi_register`, `enum vc4_hdmi_regs`, `enum vc4_hdmi_field`, `function vc4_hdmi_read`, `function vc4_hdmi_write`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.