drivers/gpu/drm/vc4/vc4_hvs.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/vc4/vc4_hvs.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/vc4/vc4_hvs.c
Extension
.c
Size
50449 bytes
Lines
1808
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct vc6_csc_coeff_entry {
	u32 csc[3][5];
};

static const struct vc6_csc_coeff_entry csc_coeffs[2][3] = {
	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
		[DRM_COLOR_YCBCR_BT601] = {
			.csc = {
				{ 0x004A8542, 0x0, 0x0066254A, 0x0, 0xFF908A0D },
				{ 0x004A8542, 0xFFE6ED5D, 0xFFCBF856, 0x0, 0x0043C9A3 },
				{ 0x004A8542, 0x00811A54, 0x0, 0x0, 0xFF759502 }
			}
		},
		[DRM_COLOR_YCBCR_BT709] = {
			.csc = {
				{ 0x004A8542, 0x0, 0x0072BC44, 0x0, 0xFF83F312 },
				{ 0x004A8542, 0xFFF25A22, 0xFFDDE4D0, 0x0, 0x00267064 },
				{ 0x004A8542, 0x00873197, 0x0, 0x0, 0xFF6F7DC0 }
			}
		},
		[DRM_COLOR_YCBCR_BT2020] = {
			.csc = {
				{ 0x004A8542, 0x0, 0x006B4A17, 0x0, 0xFF8B653F },
				{ 0x004A8542, 0xFFF402D9, 0xFFDDE4D0, 0x0, 0x0024C7AE },
				{ 0x004A8542, 0x008912CC, 0x0, 0x0, 0xFF6D9C8B }
			}
		}
	},
	[DRM_COLOR_YCBCR_FULL_RANGE] = {
		[DRM_COLOR_YCBCR_BT601] = {
			.csc = {
				{ 0x00400000, 0x0, 0x0059BA5E, 0x0, 0xFFA645A1 },
				{ 0x00400000, 0xFFE9F9AC, 0xFFD24B97, 0x0, 0x0043BABB },
				{ 0x00400000, 0x00716872, 0x0, 0x0, 0xFF8E978D }
			}
		},
		[DRM_COLOR_YCBCR_BT709] = {
			.csc = {
				{ 0x00400000, 0x0, 0x0064C985, 0x0, 0xFF9B367A },
				{ 0x00400000, 0xFFF402E1, 0xFFE20A40, 0x0, 0x0029F2DE },
				{ 0x00400000, 0x0076C226, 0x0, 0x0, 0xFF893DD9 }
			}
		},
		[DRM_COLOR_YCBCR_BT2020] = {
			.csc = {
				{ 0x00400000, 0x0, 0x005E3F14, 0x0, 0xFFA1C0EB },
				{ 0x00400000, 0xFFF577F6, 0xFFDB580F, 0x0, 0x002F2FFA },
				{ 0x00400000, 0x007868DB, 0x0, 0x0, 0xFF879724 }
			}
		}
	}
};

static int vc6_hvs_hw_init(struct vc4_hvs *hvs)
{
	const struct vc6_csc_coeff_entry *coeffs;
	unsigned int i;

	HVS_WRITE(SCALER6_CONTROL,
		  SCALER6_CONTROL_HVS_EN |
		  VC4_SET_FIELD(8, SCALER6_CONTROL_PF_LINES) |
		  VC4_SET_FIELD(15, SCALER6_CONTROL_MAX_REQS));

	/* Set HVS arbiter priority to max */
	HVS_WRITE(SCALER6(PRI_MAP0), 0xffffffff);
	HVS_WRITE(SCALER6(PRI_MAP1), 0xffffffff);

	if (hvs->vc4->gen == VC4_GEN_6_C) {
		for (i = 0; i < 6; i++) {
			coeffs = &csc_coeffs[i / 3][i % 3];

			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C03(i), coeffs->csc[0][3]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04(i), coeffs->csc[0][4]);

			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C11(i), coeffs->csc[1][1]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C12(i), coeffs->csc[1][2]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C13(i), coeffs->csc[1][3]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C14(i), coeffs->csc[1][4]);

			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C20(i), coeffs->csc[2][0]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C21(i), coeffs->csc[2][1]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C22(i), coeffs->csc[2][2]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C23(i), coeffs->csc[2][3]);
			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C24(i), coeffs->csc[2][4]);

			HVS_WRITE(CFC1_N_NL_CSC_CTRL(i), BIT(15));

Annotation

Implementation Notes