drivers/gpu/drm/vc4/vc4_vec.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/vc4/vc4_vec.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/vc4/vc4_vec.c
Extension
.c
Size
22377 bytes
Lines
850
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct vc4_vec_variant {
	u32 dac_config;
};

/* General VEC hardware state. */
struct vc4_vec {
	struct vc4_encoder encoder;
	struct drm_connector connector;

	struct platform_device *pdev;
	const struct vc4_vec_variant *variant;

	void __iomem *regs;

	struct clk *clock;

	struct drm_property *legacy_tv_mode_property;

	struct debugfs_regset32 regset;
};

#define VEC_READ(offset)								\
	({										\
		kunit_fail_current_test("Accessing a register in a unit test!\n");	\
		readl(vec->regs + (offset));						\
	})

#define VEC_WRITE(offset, val)								\
	do {										\
		kunit_fail_current_test("Accessing a register in a unit test!\n");	\
		writel(val, vec->regs + (offset));					\
	} while (0)

#define encoder_to_vc4_vec(_encoder)					\
	container_of_const(_encoder, struct vc4_vec, encoder.base)

#define connector_to_vc4_vec(_connector)				\
	container_of_const(_connector, struct vc4_vec, connector)

enum vc4_vec_tv_mode_id {
	VC4_VEC_TV_MODE_NTSC,
	VC4_VEC_TV_MODE_NTSC_J,
	VC4_VEC_TV_MODE_PAL,
	VC4_VEC_TV_MODE_PAL_M,
	VC4_VEC_TV_MODE_NTSC_443,
	VC4_VEC_TV_MODE_PAL_60,
	VC4_VEC_TV_MODE_PAL_N,
	VC4_VEC_TV_MODE_SECAM,
	VC4_VEC_TV_MODE_MONOCHROME,
};

struct vc4_vec_tv_mode {
	unsigned int mode;
	u16 expected_htotal;
	u32 config0;
	u32 config1;
	u32 custom_freq;
};

static const struct debugfs_reg32 vec_regs[] = {
	VC4_REG32(VEC_WSE_CONTROL),
	VC4_REG32(VEC_WSE_WSS_DATA),
	VC4_REG32(VEC_WSE_VPS_DATA1),
	VC4_REG32(VEC_WSE_VPS_CONTROL),
	VC4_REG32(VEC_REVID),
	VC4_REG32(VEC_CONFIG0),
	VC4_REG32(VEC_SCHPH),
	VC4_REG32(VEC_CLMP0_START),
	VC4_REG32(VEC_CLMP0_END),
	VC4_REG32(VEC_FREQ3_2),
	VC4_REG32(VEC_FREQ1_0),
	VC4_REG32(VEC_CONFIG1),
	VC4_REG32(VEC_CONFIG2),
	VC4_REG32(VEC_INTERRUPT_CONTROL),
	VC4_REG32(VEC_INTERRUPT_STATUS),
	VC4_REG32(VEC_FCW_SECAM_B),
	VC4_REG32(VEC_SECAM_GAIN_VAL),
	VC4_REG32(VEC_CONFIG3),
	VC4_REG32(VEC_STATUS0),
	VC4_REG32(VEC_MASK0),
	VC4_REG32(VEC_CFG),
	VC4_REG32(VEC_DAC_TEST),
	VC4_REG32(VEC_DAC_CONFIG),
	VC4_REG32(VEC_DAC_MISC),
};

static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
	{
		.mode = DRM_MODE_TV_MODE_NTSC,
		.expected_htotal = 858,

Annotation

Implementation Notes