drivers/gpu/drm/xe/regs/xe_engine_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/regs/xe_engine_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/regs/xe_engine_regs.h
Extension
.h
Size
9763 bytes
Lines
238
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _XE_ENGINE_REGS_H_
#define _XE_ENGINE_REGS_H_

#include <asm/page.h>

#include "regs/xe_reg_defs.h"

/*
 * These *_BASE values represent the MMIO offset where each hardware engine's
 * registers start.  The other definitions in this header are parameterized
 * macros that will take one of these values as a parameter.
 */
#define RENDER_RING_BASE			0x02000
#define BSD_RING_BASE				0x1c0000
#define BSD2_RING_BASE				0x1c4000
#define BSD3_RING_BASE				0x1d0000
#define BSD4_RING_BASE				0x1d4000
#define XEHP_BSD5_RING_BASE			0x1e0000
#define XEHP_BSD6_RING_BASE			0x1e4000
#define XEHP_BSD7_RING_BASE			0x1f0000
#define XEHP_BSD8_RING_BASE			0x1f4000
#define VEBOX_RING_BASE				0x1c8000
#define VEBOX2_RING_BASE			0x1d8000
#define XEHP_VEBOX3_RING_BASE			0x1e8000
#define XEHP_VEBOX4_RING_BASE			0x1f8000
#define COMPUTE0_RING_BASE			0x1a000
#define COMPUTE1_RING_BASE			0x1c000
#define COMPUTE2_RING_BASE			0x1e000
#define COMPUTE3_RING_BASE			0x26000
#define BLT_RING_BASE				0x22000
#define XEHPC_BCS1_RING_BASE			0x3e0000
#define XEHPC_BCS2_RING_BASE			0x3e2000
#define XEHPC_BCS3_RING_BASE			0x3e4000
#define XEHPC_BCS4_RING_BASE			0x3e6000
#define XEHPC_BCS5_RING_BASE			0x3e8000
#define XEHPC_BCS6_RING_BASE			0x3ea000
#define XEHPC_BCS7_RING_BASE			0x3ec000
#define XEHPC_BCS8_RING_BASE			0x3ee000
#define GSCCS_RING_BASE				0x11a000

#define ENGINE_ID(base)				XE_REG((base) + 0x8c)
#define   ENGINE_INSTANCE_ID			REG_GENMASK(9, 4)
#define   ENGINE_CLASS_ID			REG_GENMASK(2, 0)

#define RING_TAIL(base)				XE_REG((base) + 0x30)
#define   TAIL_ADDR				REG_GENMASK(20, 3)

#define RING_HEAD(base)				XE_REG((base) + 0x34)
#define   HEAD_ADDR				REG_GENMASK(20, 2)

#define RING_START(base)			XE_REG((base) + 0x38)

#define RING_CTL(base)				XE_REG((base) + 0x3c)
#define   RING_CTL_SIZE(size)			((size) - PAGE_SIZE) /* in bytes -> pages */

#define RING_START_UDW(base)			XE_REG((base) + 0x48)

#define RING_PSMI_CTL(base)			XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
#define   RC_SEMA_IDLE_MSG_DISABLE		REG_BIT(12)
#define   WAIT_FOR_EVENT_POWER_DOWN_DISABLE	REG_BIT(7)
#define   IDLE_MSG_DISABLE			REG_BIT(0)

#define RING_PWRCTX_MAXCNT(base)		XE_REG((base) + 0x54)
#define   IDLE_WAIT_TIME			REG_GENMASK(19, 0)

#define RING_ACTHD_UDW(base)			XE_REG((base) + 0x5c)
#define RING_DMA_FADD_UDW(base)			XE_REG((base) + 0x60)
#define RING_IPEHR(base)			XE_REG((base) + 0x68)
#define RING_INSTDONE(base)			XE_REG((base) + 0x6c)
#define RING_ACTHD(base)			XE_REG((base) + 0x74)
#define RING_DMA_FADD(base)			XE_REG((base) + 0x78)
#define RING_HWS_PGA(base)			XE_REG((base) + 0x80)
#define RING_HWSTAM(base)			XE_REG((base) + 0x98)
#define RING_MI_MODE(base)			XE_REG((base) + 0x9c)
#define RING_NOPID(base)			XE_REG((base) + 0x94)

#define FF_THREAD_MODE(base)			XE_REG((base) + 0xa0)
#define   FF_TESSELATION_DOP_GATE_DISABLE	BIT(19)

#define RING_INT_SRC_RPT_PTR(base)		XE_REG((base) + 0xa4)
#define RING_IMR(base)				XE_REG((base) + 0xa8)
#define RING_INT_STATUS_RPT_PTR(base)		XE_REG((base) + 0xac)

#define CS_INT_VEC(base)			XE_REG((base) + 0x1b8)

#define RING_EIR(base)				XE_REG((base) + 0xb0)
#define RING_EMR(base)				XE_REG((base) + 0xb4)
#define RING_ESR(base)				XE_REG((base) + 0xb8)

#define INSTPM(base)				XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED)

Annotation

Implementation Notes