drivers/gpu/drm/xe/regs/xe_gt_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/regs/xe_gt_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/regs/xe_gt_regs.h
Extension
.h
Size
25984 bytes
Lines
667
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _XE_GT_REGS_H_
#define _XE_GT_REGS_H_

#include "regs/xe_reg_defs.h"

/*
 * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
 * for the media GT.  xe_mmio and xe_gt_mcr functions will automatically
 * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
 */
#define MEDIA_GT_GSI_OFFSET				0x380000
#define MEDIA_GT_GSI_LENGTH				0x40000

/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
#define MTL_MIRROR_TARGET_WP1				XE_REG(0xc60)
#define   MTL_CAGF_MASK					REG_GENMASK(8, 0)
#define   MTL_CC_MASK					REG_GENMASK(12, 9)
#define   MTL_CRST					0xf

/* RPM unit config (Gen8+) */
#define RPM_CONFIG0					XE_REG(0xd00)
#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)
#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ		0
#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ		3
#define   RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)

#define FORCEWAKE_ACK_MEDIA_VDBOX(n)		XE_REG(0xd50 + (n) * 4)
#define FORCEWAKE_ACK_MEDIA_VEBOX(n)		XE_REG(0xd70 + (n) * 4)
#define FORCEWAKE_ACK_RENDER			XE_REG(0xd84)

#define GMD_ID					XE_REG(0xd8c)
#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
/*
 * Spec defines these bits as "Reserved", but then make them assume some
 * meaning that depends on the ARCH. To avoid any confusion, call them
 * SUBIP_FLAG_MASK.
 */
#define   GMD_ID_SUBIP_FLAG_MASK		REG_GENMASK(13, 6)
#define   GMD_ID_REVID				REG_GENMASK(5, 0)

#define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
#define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)

#define STEER_SEMAPHORE				XE_REG(0xfd0)
#define MTL_MCR_SELECTOR			XE_REG(0xfd4)
#define SF_MCR_SELECTOR				XE_REG(0xfd8)
#define MCR_SELECTOR				XE_REG(0xfdc)
#define GAM_MCR_SELECTOR			XE_REG(0xfe0)
#define   MCR_MULTICAST				REG_BIT(31)
#define   MCR_SLICE_MASK			REG_GENMASK(30, 27)
#define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)
#define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
#define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
#define   MTL_MCR_GROUPID			REG_GENMASK(12, 8)
#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)

#define PS_INVOCATION_COUNT			XE_REG(0x2348)

#define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)
#define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)
#define   LE_SSE_MASK				REG_GENMASK(18, 17)
#define   LE_SSE(value)				REG_FIELD_PREP(LE_SSE_MASK, value)
#define   LE_COS_MASK				REG_GENMASK(16, 15)
#define   LE_SCF_MASK				REG_BIT(14)
#define   LE_SCF(value)				REG_FIELD_PREP(LE_SCF_MASK, value)
#define   LE_PFM_MASK				REG_GENMASK(13, 11)
#define   LE_PFM(value)				REG_FIELD_PREP(LE_PFM_MASK, value)
#define   LE_SCC_MASK				REG_GENMASK(10, 8)
#define   LE_SCC(value)				REG_FIELD_PREP(LE_SCC_MASK, value)
#define   LE_RSC_MASK				REG_BIT(7)
#define   LE_RSC(value)				REG_FIELD_PREP(LE_RSC_MASK, value)
#define   LE_AOM_MASK				REG_BIT(6)
#define   LE_AOM(value)				REG_FIELD_PREP(LE_AOM_MASK, value)
#define   LE_LRUM_MASK				REG_GENMASK(5, 4)
#define   LE_LRUM(value)			REG_FIELD_PREP(LE_LRUM_MASK, value)
#define   LE_TGT_CACHE_MASK			REG_GENMASK(3, 2)
#define   LE_TGT_CACHE(value)			REG_FIELD_PREP(LE_TGT_CACHE_MASK, value)
#define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)
#define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)

#define STATELESS_COMPRESSION_CTRL		XE_REG_MCR(0x4148)
#define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)

#define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)
#define   EN_CMP_1WCOH				REG_BIT(15)
#define   CG_DIS_CNTLBUS			REG_BIT(6)

Annotation

Implementation Notes