drivers/gpu/drm/xe/xe_execlist.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_execlist.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_execlist.h- Extension
.h- Size
- 490 bytes
- Lines
- 22
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
xe_execlist_types.h
Detected Declarations
struct xe_devicestruct xe_gt
Annotated Snippet
#ifndef _XE_EXECLIST_H_
#define _XE_EXECLIST_H_
#include "xe_execlist_types.h"
struct xe_device;
struct xe_gt;
#define xe_execlist_port_assert_held(port) lockdep_assert_held(&(port)->lock)
int xe_execlist_init(struct xe_gt *gt);
struct xe_execlist_port *xe_execlist_port_create(struct xe_device *xe,
struct xe_hw_engine *hwe);
void xe_execlist_port_destroy(struct xe_execlist_port *port);
#endif
Annotation
- Immediate include surface: `xe_execlist_types.h`.
- Detected declarations: `struct xe_device`, `struct xe_gt`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.