drivers/gpu/drm/xe/xe_ggtt_types.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_ggtt_types.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_ggtt_types.h- Extension
.h- Size
- 476 bytes
- Lines
- 22
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hdrm/drm_mm.h
Detected Declarations
struct xe_ggttstruct xe_ggtt_node
Annotated Snippet
#ifndef _XE_GGTT_TYPES_H_
#define _XE_GGTT_TYPES_H_
#include <linux/types.h>
#include <drm/drm_mm.h>
struct xe_ggtt;
struct xe_ggtt_node;
typedef void (*xe_ggtt_set_pte_fn)(struct xe_ggtt *ggtt, u64 addr, u64 pte);
typedef void (*xe_ggtt_transform_cb)(struct xe_ggtt *ggtt,
struct xe_ggtt_node *node,
u64 pte_flags,
xe_ggtt_set_pte_fn set_pte, void *arg);
#endif
Annotation
- Immediate include surface: `linux/types.h`, `drm/drm_mm.h`.
- Detected declarations: `struct xe_ggtt`, `struct xe_ggtt_node`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.