drivers/gpu/drm/xe/xe_gt_mcr.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_gt_mcr.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/xe_gt_mcr.c
Extension
.c
Size
30202 bytes
Lines
908
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (MEDIA_VER(xe) >= 30) {
			gt->steering[OADDRM].ranges = xe2lpm_gpmxmt_steering_table;
			gt->steering[INSTANCE0].ranges = xe3lpm_instance0_steering_table;
		} else if (MEDIA_VERx100(xe) >= 1301) {
			gt->steering[OADDRM].ranges = xe2lpm_gpmxmt_steering_table;
			gt->steering[INSTANCE0].ranges = xe2lpm_instance0_steering_table;
		} else {
			gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
		}
	} else {
		if (GRAPHICS_VERx100(xe) == 3511) {
			gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
			gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
			gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
			gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table;
			gt->steering[NODE].ranges = xe2_node_steering_table;
		} else if (GRAPHICS_VERx100(xe) >= 3510) {
			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
			gt->steering[INSTANCE0].ranges = xe3p_lpg_instance0_steering_table;
		} else if (GRAPHICS_VER(xe) >= 20) {
			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
			gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
			gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;
			gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table;
			gt->steering[NODE].ranges = xe2_node_steering_table;
		} else if (GRAPHICS_VERx100(xe) >= 1270) {
			gt->steering[INSTANCE0].ranges = xelpg_instance0_steering_table;
			gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table;
			gt->steering[DSS].ranges = xelpg_dss_steering_table;
		} else if (xe->info.platform == XE_PVC) {
			gt->steering[INSTANCE0].ranges = xehpc_instance0_steering_table;
			gt->steering[DSS].ranges = xehpc_dss_steering_table;
		} else if (xe->info.platform == XE_DG2) {
			gt->steering[L3BANK].ranges = xehp_l3bank_steering_table;
			gt->steering[MSLICE].ranges = xehp_mslice_steering_table;
			gt->steering[LNCF].ranges = xehp_lncf_steering_table;
			gt->steering[DSS].ranges = xehp_dss_steering_table;
			gt->steering[IMPLICIT_STEERING].ranges = dg2_implicit_steering_table;
		} else {
			gt->steering[L3BANK].ranges = xelp_l3bank_steering_table;
			gt->steering[DSS].ranges = xelp_dss_steering_table;
		}
	}

	/* Mark instance 0 as initialized, we need this early for VRAM and CCS probe. */
	gt->steering[INSTANCE0].initialized = true;
}
EXPORT_SYMBOL_IF_KUNIT(xe_gt_mcr_init_early);

/**
 * xe_gt_mcr_init - Normal initialization of the MCR support
 * @gt: GT structure
 *
 * Perform normal initialization of the MCR for all usages.
 */
void xe_gt_mcr_init(struct xe_gt *gt)
{
	/* Select non-terminated steering target for each type */
	for (int i = 0; i < NUM_STEERING_TYPES; i++) {
		gt->steering[i].initialized = true;
		if (gt->steering[i].ranges && xe_steering_types[i].init)
			xe_steering_types[i].init(gt);
	}
}

/**
 * xe_gt_mcr_set_implicit_defaults - Initialize steer control registers
 * @gt: GT structure
 *
 * Some register ranges don't need to have their steering control registers
 * changed on each access - it's sufficient to set them once on initialization.
 * This function sets those registers for each platform *
 */
void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
{
	struct xe_device *xe = gt_to_xe(gt);

	if (IS_SRIOV_VF(xe))
		return;

	if (xe->info.platform == XE_DG2) {
		u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
			REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);

		xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, steer_val);
		xe_mmio_write32(&gt->mmio, SF_MCR_SELECTOR, steer_val);
		/*
		 * For GAM registers, all reads should be directed to instance 1
		 * (unicast reads against other instances are not allowed),
		 * and instance 1 is already the hardware's default steering

Annotation

Implementation Notes