drivers/gpu/drm/xe/xe_gt_mcr.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_gt_mcr.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_gt_mcr.h- Extension
.h- Size
- 2542 bytes
- Lines
- 75
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
regs/xe_reg_defs.hxe_gt_topology.h
Detected Declarations
struct drm_printerstruct xe_gt
Annotated Snippet
#ifndef _XE_GT_MCR_H_
#define _XE_GT_MCR_H_
#include "regs/xe_reg_defs.h"
#include "xe_gt_topology.h"
struct drm_printer;
struct xe_gt;
void xe_gt_mcr_init_early(struct xe_gt *gt);
void xe_gt_mcr_init(struct xe_gt *gt);
void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);
u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,
int group, int instance);
u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr mcr_reg);
void xe_gt_mcr_unicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,
u32 value, int group, int instance);
void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,
u32 value);
bool xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg);
bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
struct xe_reg_mcr reg_mcr,
u8 *group, u8 *instance);
void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
void xe_gt_mcr_get_dss_steering(const struct xe_gt *gt,
unsigned int dss, u16 *group, u16 *instance);
/*
* Loop over each DSS and determine the group and instance IDs that
* should be used to steer MCR accesses toward this DSS.
* @dss: DSS ID to obtain steering for
* @gt: GT structure
* @group: steering group ID, data type: u16
* @instance: steering instance ID, data type: u16
*/
#define for_each_dss_steering(dss, gt, group, instance) \
for_each_dss((dss), (gt)) \
for_each_if((xe_gt_mcr_get_dss_steering((gt), (dss), &(group), &(instance)), true))
/*
* Loop over each DSS available for geometry and determine the group and
* instance IDs that should be used to steer MCR accesses toward this DSS.
* @dss: DSS ID to obtain steering for
* @gt: GT structure
* @group: steering group ID, data type: u16
* @instance: steering instance ID, data type: u16
*/
#define for_each_geometry_dss(dss, gt, group, instance) \
for_each_dss_steering(dss, gt, group, instance) \
if (xe_gt_has_geometry_dss(gt, dss))
/*
* Loop over each DSS available for compute and determine the group and
* instance IDs that should be used to steer MCR accesses toward this DSS.
* @dss: DSS ID to obtain steering for
* @gt: GT structure
* @group: steering group ID, data type: u16
* @instance: steering instance ID, data type: u16
*/
#define for_each_compute_dss(dss, gt, group, instance) \
for_each_dss_steering(dss, gt, group, instance) \
if (xe_gt_has_compute_dss(gt, dss))
#endif /* _XE_GT_MCR_H_ */
Annotation
- Immediate include surface: `regs/xe_reg_defs.h`, `xe_gt_topology.h`.
- Detected declarations: `struct drm_printer`, `struct xe_gt`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.