drivers/gpu/drm/xe/xe_gt_types.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_gt_types.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/xe_gt_types.h
Extension
.h
Size
11348 bytes
Lines
385
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct xe_gt {
	/** @tile: Backpointer to GT's tile */
	struct xe_tile *tile;

	/** @info: GT info */
	struct {
		/** @info.type: type of GT */
		enum xe_gt_type type;
		/** @info.reference_clock: clock frequency */
		u32 reference_clock;
		/** @info.timestamp_base: GT timestamp base */
		u32 timestamp_base;
		/**
		 * @info.engine_mask: mask of engines present on GT. Some of
		 * them may be reserved in runtime and not available for user.
		 * See @user_engines.mask
		 */
		u64 engine_mask;
		/** @info.gmdid: raw GMD_ID value from hardware */
		u32 gmdid;
		/**
		 * @info.multi_queue_engine_class_mask: Bitmask of engine classes with
		 * multi queue support enabled.
		 */
		u16 multi_queue_engine_class_mask;
		/** @info.id: Unique ID of this GT within the PCI Device */
		u8 id;
		/** @info.has_indirect_ring_state: GT has indirect ring state support */
		u8 has_indirect_ring_state:1;
		/**
		 * @info.has_xe2_blt_instructions: GT supports Xe2-style MEM_SET
		 * and MEM_COPY blitter functionality.  Note that despite the
		 * name, some Xe1 platforms may also support this "Xe2-style"
		 * feature.
		 */
		u8 has_xe2_blt_instructions:1;
		/**
		 * @info.num_geometry_xecore_fuse_regs: Number of 32b-bit fuse
		 * registers the geometry XeCore mask spans.
		 */
		u8 num_geometry_xecore_fuse_regs;
		/**
		 * @info.num_compute_xecore_fuse_regs: Number of 32b-bit fuse
		 * registers the compute XeCore mask spans.
		 */
		u8 num_compute_xecore_fuse_regs;
	} info;

#if IS_ENABLED(CONFIG_DEBUG_FS)
	/** @stats: GT stats */
	struct xe_gt_stats __percpu *stats;
#endif

	/**
	 * @mmio: mmio info for GT.  All GTs within a tile share the same
	 * register space, but have their own copy of GSI registers at a
	 * specific offset.
	 */
	struct xe_mmio mmio;

	/**
	 * @pm: power management info for GT.  The driver uses the GT's
	 * "force wake" interface to wake up specific parts of the GT hardware
	 * from C6 sleep states and ensure the hardware remains awake while it
	 * is being actively used.
	 */
	struct {
		/** @pm.fw: force wake for GT */
		struct xe_force_wake fw;
	} pm;

	/** @sriov: virtualization data related to GT */
	union {
		/** @sriov.pf: PF data. Valid only if driver is running as PF */
		struct xe_gt_sriov_pf pf;
		/** @sriov.vf: VF data. Valid only if driver is running as VF */
		struct xe_gt_sriov_vf vf;
	} sriov;

	/**
	 * @reg_sr: table with registers to be restored on GT init/resume/reset
	 */
	struct xe_reg_sr reg_sr;

	/** @reset: state for GT resets */
	struct {
		/**
		 * @reset.worker: work so GT resets can done async allowing to reset
		 * code to safely flush all code paths
		 */

Annotation

Implementation Notes