drivers/gpu/drm/xe/xe_guc_fwif.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_guc_fwif.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/xe_guc_fwif.h
Extension
.h
Size
8686 bytes
Lines
321
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct guc_klv_generic_dw_t {
	u32 kl;
	u32 value;
} __packed;

/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
struct guc_update_exec_queue_policy_header {
	u32 action;
	u32 guc_id;
} __packed;

struct guc_update_exec_queue_policy {
	struct guc_update_exec_queue_policy_header header;
	struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
} __packed;

/* GUC_CTL_* - Parameters for loading the GuC */
#define GUC_CTL_LOG_PARAMS		0
#define   GUC_LOG_VALID			BIT(0)
#define   GUC_LOG_NOTIFY_ON_HALF_FULL	BIT(1)
#define   GUC_LOG_CAPTURE_ALLOC_UNITS	BIT(2)
#define   GUC_LOG_LOG_ALLOC_UNITS	BIT(3)
#define   GUC_LOG_CRASH_DUMP		REG_GENMASK(5, 4)
#define   GUC_LOG_EVENT_DATA		REG_GENMASK(9, 6)
#define   GUC_LOG_STATE_CAPTURE		REG_GENMASK(11, 10)
#define   GUC_LOG_BUF_ADDR		REG_GENMASK(31, 12)

#define GUC_CTL_WA			1
#define   GUC_WA_GAM_CREDITS		BIT(10)
#define   GUC_WA_DUAL_QUEUE		BIT(11)
#define   GUC_WA_RCS_RESET_BEFORE_RC6	BIT(13)
#define   GUC_WA_CONTEXT_ISOLATION	BIT(15)
#define   GUC_WA_PRE_PARSER		BIT(14)
#define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)
#define   GUC_WA_POLLCS			BIT(18)
#define   GUC_WA_RENDER_RST_RC6_EXIT	BIT(19)
#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)
#define   GUC_WA_ENABLE_TSC_CHECK_ON_RC6	BIT(22)
#define   GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6	BIT(25)

#define GUC_CTL_FEATURE			2
#define   GUC_CTL_ENABLE_SLPC		BIT(2)
#define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
#define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
#define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
#define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)

#define GUC_CTL_DEBUG			3
#define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
#define	  GUC_LOG_VERBOSITY_MAX		3
#define	  GUC_LOG_DESTINATION		REG_GENMASK(5, 4)
#define   GUC_LOG_DISABLED		BIT(6)
#define   GUC_PROFILE_ENABLED		BIT(7)

#define GUC_CTL_ADS			4
#define   GUC_ADS_ADDR			REG_GENMASK(21, 1)

#define GUC_CTL_DEVID			5

#define GUC_CTL_MAX_DWORDS		14

/* Scheduling policy settings */

#define GLOBAL_POLICY_MAX_NUM_WI 15

/* Don't reset an engine upon preemption failure */
#define GLOBAL_POLICY_DISABLE_ENGINE_RESET				BIT(0)

#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000

struct guc_policies {
	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
	/*
	 * In micro seconds. How much time to allow before DPC processing is
	 * called back via interrupt (to prevent DPC queue drain starving).
	 * Typically 1000s of micro seconds (example only, not granularity).
	 */
	u32 dpc_promote_time;

	/* Must be set to take these new values. */
	u32 is_valid;

	/*
	 * Max number of WIs to process per call. A large value may keep CS
	 * idle.
	 */
	u32 max_num_work_items;

	u32 global_flags;

Annotation

Implementation Notes