drivers/gpu/drm/xe/xe_guc_pc.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_guc_pc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_guc_pc.c- Extension
.c- Size
- 35002 bytes
- Lines
- 1442
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
xe_guc_pc.hlinux/cleanup.hlinux/delay.hlinux/iopoll.hlinux/jiffies.hlinux/ktime.hlinux/wait_bit.hdrm/drm_managed.hdrm/drm_print.hgenerated/xe_device_wa_oob.hgenerated/xe_wa_oob.habi/guc_actions_slpc_abi.hregs/xe_gt_regs.hregs/xe_regs.hxe_bo.hxe_device.hxe_force_wake.hxe_gt.hxe_gt_idle.hxe_gt_printk.hxe_gt_throttle.hxe_gt_types.hxe_guc.hxe_guc_ct.hxe_map.hxe_mmio.hxe_pcode.hxe_pm.hxe_sriov.hxe_wa.h
Detected Declarations
function Conservationfunction FIELD_PREPfunction wait_for_flush_completefunction wait_for_act_freq_max_limitfunction pc_action_resetfunction pc_action_query_task_statefunction pc_action_set_paramfunction pc_action_unset_paramfunction xe_guc_pc_action_set_paramfunction xe_guc_pc_action_unset_paramfunction decode_freqfunction encode_freqfunction pc_get_min_freqfunction pc_set_manual_rp_ctrlfunction pc_set_cur_freqfunction pc_set_min_freqfunction pc_get_max_freqfunction pc_set_max_freqfunction mtl_get_rpa_freqfunction mtl_get_rpe_freqfunction pvc_get_rpa_freqfunction tgl_get_rpa_freqfunction pvc_get_rpe_freqfunction tgl_get_rpe_freqfunction xe_guc_pc_get_act_freqfunction get_cur_freqfunction xe_guc_pc_get_cur_freq_fwfunction xe_guc_pc_get_cur_freqfunction xe_guc_pc_get_rp0_freqfunction xe_guc_pc_get_rpa_freqfunction xe_guc_pc_get_rpe_freqfunction xe_guc_pc_get_rpn_freqfunction xe_guc_pc_get_min_freq_lockedfunction xe_guc_pc_get_min_freqfunction xe_guc_pc_set_min_freq_lockedfunction xe_guc_pc_set_min_freqfunction xe_guc_pc_get_max_freq_lockedfunction xe_guc_pc_get_max_freqfunction xe_guc_pc_set_max_freq_lockedfunction xe_guc_pc_set_max_freqfunction xe_guc_pc_c_statusfunction xe_guc_pc_rc6_residencyfunction xe_guc_pc_mc6_residencyfunction mtl_init_fused_rp_valuesfunction tgl_init_fused_rp_valuesfunction pc_init_fused_rp_valuesfunction pc_max_freq_capfunction xe_guc_pc_raise_unslice
Annotated Snippet
if (ret) {
xe_gt_err_once(gt, "Failed to cap max freq on flush to %u, %pe\n",
BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
return;
}
atomic_set(&pc->flush_freq_limit, 1);
/*
* If user has previously changed max freq, stash that value to
* restore later, otherwise use the current max. New user
* requests wait on flush.
*/
if (pc->user_requested_max != 0)
pc->stashed_max_freq = pc->user_requested_max;
else
pc->stashed_max_freq = max_freq;
}
/*
* Wait for actual freq to go below the flush cap: even if the previous
* max was below cap, the current one might still be above it
*/
ret = wait_for_act_freq_max_limit(pc, BMG_MERT_FLUSH_FREQ_CAP);
if (ret)
xe_gt_err_once(gt, "Actual freq did not reduce to %u, %pe\n",
BMG_MERT_FLUSH_FREQ_CAP, ERR_PTR(ret));
}
/**
* xe_guc_pc_remove_flush_freq_limit() - Remove max GT freq limit after L2 flush completes.
* @pc: the xe_guc_pc object
*
* Retrieve the previous GT max frequency value.
*/
void xe_guc_pc_remove_flush_freq_limit(struct xe_guc_pc *pc)
{
struct xe_gt *gt = pc_to_gt(pc);
int ret = 0;
if (!needs_flush_freq_limit(pc))
return;
if (!atomic_read(&pc->flush_freq_limit))
return;
mutex_lock(&pc->freq_lock);
ret = pc_set_max_freq(>->uc.guc.pc, pc->stashed_max_freq);
if (ret)
xe_gt_err_once(gt, "Failed to restore max freq %u:%d",
pc->stashed_max_freq, ret);
atomic_set(&pc->flush_freq_limit, 0);
mutex_unlock(&pc->freq_lock);
wake_up_var(&pc->flush_freq_limit);
}
static int pc_set_mert_freq_cap(struct xe_guc_pc *pc)
{
int ret;
if (!XE_GT_WA(pc_to_gt(pc), 22019338487))
return 0;
guard(mutex)(&pc->freq_lock);
/*
* Get updated min/max and stash them.
*/
ret = xe_guc_pc_get_min_freq_locked(pc, &pc->stashed_min_freq);
if (!ret)
ret = xe_guc_pc_get_max_freq_locked(pc, &pc->stashed_max_freq);
if (ret)
return ret;
/*
* Ensure min and max are bound by MERT_FREQ_CAP until driver loads.
*/
ret = pc_set_min_freq(pc, min(xe_guc_pc_get_rpe_freq(pc), pc_max_freq_cap(pc)));
if (!ret)
ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc)));
return ret;
}
/**
* xe_guc_pc_restore_stashed_freq - Set min/max back to stashed values
* @pc: The GuC PC
*
Annotation
- Immediate include surface: `xe_guc_pc.h`, `linux/cleanup.h`, `linux/delay.h`, `linux/iopoll.h`, `linux/jiffies.h`, `linux/ktime.h`, `linux/wait_bit.h`, `drm/drm_managed.h`.
- Detected declarations: `function Conservation`, `function FIELD_PREP`, `function wait_for_flush_complete`, `function wait_for_act_freq_max_limit`, `function pc_action_reset`, `function pc_action_query_task_state`, `function pc_action_set_param`, `function pc_action_unset_param`, `function xe_guc_pc_action_set_param`, `function xe_guc_pc_action_unset_param`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.