drivers/gpu/drm/xe/xe_hw_fence_types.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_hw_fence_types.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_hw_fence_types.h- Extension
.h- Size
- 2030 bytes
- Lines
- 76
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-fence.hlinux/iosys-map.hlinux/irq_work.hlinux/list.hlinux/spinlock.h
Detected Declarations
struct xe_devicestruct xe_gtstruct xe_hw_fence_irqstruct xe_hw_fence_ctxstruct xe_hw_fence
Annotated Snippet
struct xe_hw_fence_irq {
/** @lock: protects all xe_hw_fences + pending list */
spinlock_t lock;
/** @work: IRQ worker run to signal the fences */
struct irq_work work;
/** @pending: list of pending xe_hw_fences */
struct list_head pending;
/** @enabled: fence signaling enabled */
bool enabled;
};
#define MAX_FENCE_NAME_LEN 16
/**
* struct xe_hw_fence_ctx - hardware fence context
*
* The context for a hardware fence. 1 to 1 relationship with xe_engine. Points
* to a xe_hw_fence_irq, maintains serial seqno.
*/
struct xe_hw_fence_ctx {
/** @gt: GT structure of hardware fence context */
struct xe_gt *gt;
/** @irq: fence irq handler */
struct xe_hw_fence_irq *irq;
/** @dma_fence_ctx: dma fence context for hardware fence */
u64 dma_fence_ctx;
/** @next_seqno: next seqno for hardware fence */
u32 next_seqno;
/** @name: name of hardware fence context */
char name[MAX_FENCE_NAME_LEN];
};
/**
* struct xe_hw_fence - hardware fence
*
* Used to indicate a xe_sched_job is complete via a seqno written to memory.
* Signals on error or seqno past.
*/
struct xe_hw_fence {
/** @dma: base dma fence for hardware fence context */
struct dma_fence dma;
/** @xe: Xe device for hw fence driver name */
struct xe_device *xe;
/** @name: name of hardware fence context */
char name[MAX_FENCE_NAME_LEN];
/** @seqno_map: I/O map for seqno */
struct iosys_map seqno_map;
/** @irq_link: Link in struct xe_hw_fence_irq.pending */
struct list_head irq_link;
};
#endif
Annotation
- Immediate include surface: `linux/dma-fence.h`, `linux/iosys-map.h`, `linux/irq_work.h`, `linux/list.h`, `linux/spinlock.h`.
- Detected declarations: `struct xe_device`, `struct xe_gt`, `struct xe_hw_fence_irq`, `struct xe_hw_fence_ctx`, `struct xe_hw_fence`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.