drivers/gpu/drm/xe/xe_irq.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_irq.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/xe_irq.c
Extension
.c
Size
26721 bytes
Lines
1054
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) {
			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
		}
	} else {
		common_mask = GT_MI_USER_INTERRUPT |
			      GT_CS_MASTER_ERROR_INTERRUPT |
			      GT_CONTEXT_SWITCH_INTERRUPT |
			      GT_WAIT_SEMAPHORE_INTERRUPT;
	}

	rcs_mask |= common_mask;
	bcs_mask |= common_mask;
	vcs_mask |= common_mask;
	vecs_mask |= common_mask;
	ccs_mask |= common_mask;

	if (xe_gt_is_main_type(gt)) {
		/*
		 * For enabling the interrupts, the information about fused off
		 * engines doesn't matter much, but this also allows to check if
		 * the engine is available architecturally in the platform
		 */
		u32 ccs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);

		/* Enable interrupts for each engine class */
		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,
				REG_FIELD_PREP(ENGINE1_MASK, rcs_mask) |
				REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
		if (ccs_fuse_mask)
			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,
					REG_FIELD_PREP(ENGINE1_MASK, ccs_mask));

		/* Unmask interrupts for each engine instance */
		val = ~REG_FIELD_PREP(ENGINE1_MASK, rcs_mask);
		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);
		val = ~REG_FIELD_PREP(ENGINE1_MASK, bcs_mask);
		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);

		val = ~(REG_FIELD_PREP(ENGINE1_MASK, bcs_mask) |
			REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);
		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);
		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);
		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);

		val = ~(REG_FIELD_PREP(ENGINE1_MASK, ccs_mask) |
			REG_FIELD_PREP(ENGINE0_MASK, ccs_mask));
		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);
		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);
	}

	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
		u32 vcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_DECODE);
		u32 vecs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE);
		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);

		/* Enable interrupts for each engine class */
		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,
				REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
				REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));

		/* Unmask interrupts for each engine instance */
		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
		if (vcs_fuse_mask & (BIT(0) | BIT(1)))
			xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
		if (vcs_fuse_mask & (BIT(2) | BIT(3)))
			xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
		if (vcs_fuse_mask & (BIT(4) | BIT(5)))
			xe_mmio_write32(mmio, VCS4_VCS5_INTR_MASK, val);
		if (vcs_fuse_mask & (BIT(6) | BIT(7)))
			xe_mmio_write32(mmio, VCS6_VCS7_INTR_MASK, val);

		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) |
			REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
		if (vecs_fuse_mask & (BIT(0) | BIT(1)))
			xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
		if (vecs_fuse_mask & (BIT(2) | BIT(3)))
			xe_mmio_write32(mmio, VECS2_VECS3_INTR_MASK, val);

		/*
		 * the heci2 interrupt is enabled via the same register as the

Annotation

Implementation Notes