drivers/gpu/drm/xe/xe_lrc.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_lrc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_lrc.c- Extension
.c- Size
- 75911 bytes
- Lines
- 2800
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
xe_lrc.hgenerated/xe_wa_oob.hlinux/ascii85.hlinux/panic.hinstructions/xe_mi_commands.hinstructions/xe_gfxpipe_commands.hinstructions/xe_gfx_state_commands.hregs/xe_engine_regs.hregs/xe_gt_regs.hregs/xe_lrc_layout.hxe_bb.hxe_bo.hxe_configfs.hxe_device.hxe_drm_client.hxe_exec_queue.hxe_exec_queue_types.hxe_gt.hxe_gt_clock.hxe_gt_printk.hxe_hw_fence.hxe_map.hxe_memirq.hxe_mmio.hxe_ring_ops.hxe_sriov.hxe_trace_lrc.hxe_vm.hxe_wa.h
Detected Declarations
struct bo_setupstruct bo_setup_statestruct instr_statefunction lrc_to_xefunction gt_engine_needs_indirect_ctxfunction xe_gt_lrc_hang_replay_sizefunction xe_gt_lrc_sizefunction set_offsetsfunction set_context_controlfunction set_memory_based_intrfunction xe_lrc_has_indirect_ring_statefunction __xe_lrc_ring_offsetfunction xe_lrc_pphwsp_offsetfunction xe_lrc_regs_offsetfunction xe_lrc_reg_sizefunction xe_lrc_engine_state_sizefunction __xe_lrc_seqno_offsetfunction __xe_lrc_start_seqno_offsetfunction __xe_lrc_ctx_job_timestamp_offsetfunction __xe_lrc_parallel_offsetfunction __xe_lrc_engine_id_offsetfunction __xe_lrc_ctx_timestamp_offsetfunction __xe_lrc_ctx_timestamp_udw_offsetfunction __xe_lrc_queue_timestamp_offsetfunction __xe_lrc_queue_timestamp_udw_offsetfunction __xe_lrc_indirect_ring_offsetfunction __xe_lrc_indirect_ctx_offsetfunction __xe_lrc_wa_bb_offsetfunction xe_lrc_ctx_timestamp_ggtt_addrfunction xe_lrc_ctx_timestamp_udw_ggtt_addrfunction xe_lrc_ctx_timestampfunction xe_lrc_queue_timestampfunction xe_lrc_ctx_job_timestamp_ggtt_addrfunction xe_lrc_ctx_job_timestampfunction xe_lrc_ggtt_addrfunction xe_lrc_indirect_ring_ggtt_addrfunction xe_lrc_read_indirect_ctx_regfunction xe_lrc_write_indirect_ctx_regfunction xe_lrc_read_ctx_regfunction xe_lrc_write_ctx_regfunction xe_default_lrc_update_memirq_regs_with_addressfunction xe_lrc_update_memirq_regs_with_addressfunction xe_lrc_set_ppgttfunction xe_lrc_finishfunction wa_bb_setup_utilizationfunction setup_timestamp_wafunction setup_configfs_post_ctx_restore_bbfunction setup_configfs_mid_ctx_restore_bb
Annotated Snippet
struct bo_setup {
ssize_t (*setup)(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
u32 *batch, size_t max_size);
};
struct bo_setup_state {
/* Input: */
struct xe_lrc *lrc;
struct xe_hw_engine *hwe;
size_t max_size;
size_t reserve_dw;
unsigned int offset;
const struct bo_setup *funcs;
unsigned int num_funcs;
/* State: */
u32 *buffer;
u32 *ptr;
unsigned int written;
};
static int setup_bo(struct bo_setup_state *state)
{
ssize_t remain;
if (state->lrc->bo->vmap.is_iomem) {
xe_gt_assert(state->hwe->gt, state->buffer);
state->ptr = state->buffer;
} else {
state->ptr = state->lrc->bo->vmap.vaddr + state->offset;
}
remain = state->max_size / sizeof(u32);
for (size_t i = 0; i < state->num_funcs; i++) {
ssize_t len = state->funcs[i].setup(state->lrc, state->hwe,
state->ptr, remain);
remain -= len;
/*
* Caller has asked for at least reserve_dw to remain unused.
*/
if (len < 0 ||
xe_gt_WARN_ON(state->lrc->gt, remain < state->reserve_dw))
goto fail;
state->ptr += len;
state->written += len;
}
return 0;
fail:
return -ENOSPC;
}
static void finish_bo(struct bo_setup_state *state)
{
if (!state->lrc->bo->vmap.is_iomem)
return;
xe_map_memcpy_to(gt_to_xe(state->lrc->gt), &state->lrc->bo->vmap,
state->offset, state->buffer,
state->written * sizeof(u32));
}
/**
* xe_lrc_setup_wa_bb_with_scratch - Execute all wa bb setup callbacks.
* @lrc: the &xe_lrc struct instance
* @hwe: the &xe_hw_engine struct instance
* @scratch: preallocated scratch buffer for temporary storage
* Return: 0 on success, negative error code on failure
*/
int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe, u32 *scratch)
{
static const struct bo_setup funcs[] = {
{ .setup = setup_timestamp_wa },
{ .setup = setup_invalidate_state_cache_wa },
{ .setup = setup_utilization_wa },
{ .setup = setup_configfs_post_ctx_restore_bb },
};
struct bo_setup_state state = {
.lrc = lrc,
.hwe = hwe,
.max_size = LRC_WA_BB_SIZE,
.buffer = scratch,
.reserve_dw = 1,
.offset = __xe_lrc_wa_bb_offset(lrc),
.funcs = funcs,
Annotation
- Immediate include surface: `xe_lrc.h`, `generated/xe_wa_oob.h`, `linux/ascii85.h`, `linux/panic.h`, `instructions/xe_mi_commands.h`, `instructions/xe_gfxpipe_commands.h`, `instructions/xe_gfx_state_commands.h`, `regs/xe_engine_regs.h`.
- Detected declarations: `struct bo_setup`, `struct bo_setup_state`, `struct instr_state`, `function lrc_to_xe`, `function gt_engine_needs_indirect_ctx`, `function xe_gt_lrc_hang_replay_size`, `function xe_gt_lrc_size`, `function set_offsets`, `function set_context_control`, `function set_memory_based_intr`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.