drivers/gpu/drm/xe/xe_mocs.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_mocs.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/xe_mocs.c
Extension
.c
Size
22935 bytes
Lines
832
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct xe_mocs_entry {
	u32 control_value;
	u16 l3cc_value;
	u16 used;
};

struct xe_mocs_info;

struct xe_mocs_ops {
	void (*dump)(struct xe_mocs_info *mocs, unsigned int flags,
		     struct xe_gt *gt, struct drm_printer *p);
};

struct xe_mocs_info {
	/*
	 * Size of the spec's suggested MOCS programming table.  The list of
	 * table entries from the spec can potentially be smaller than the
	 * number of hardware registers used to program the MOCS table; in such
	 * cases the registers for the remaining indices will be programmed to
	 * match unused_entries_index.
	 */
	unsigned int table_size;
	/* Number of MOCS entries supported by the hardware */
	unsigned int num_mocs_regs;
	const struct xe_mocs_entry *table;
	const struct xe_mocs_ops *ops;
	u8 uc_index;
	u8 wb_index;
	u8 unused_entries_index;
};

/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
#define IG_PAT				REG_BIT(8)
#define L3_CACHE_POLICY_MASK		REG_GENMASK(5, 4)
#define L4_CACHE_POLICY_MASK		REG_GENMASK(3, 2)

/* Helper defines */
#define XELP_NUM_MOCS_ENTRIES	64  /* 63-64 are reserved, but configured. */
#define PVC_NUM_MOCS_ENTRIES	3
#define MTL_NUM_MOCS_ENTRIES	16
#define XE2_NUM_MOCS_ENTRIES	16

/* (e)LLC caching options */
/*
 * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
 * the same as LE_UC
 */
#define LE_0_PAGETABLE		LE_CACHEABILITY(0)
#define LE_1_UC			LE_CACHEABILITY(1)
#define LE_2_WT			LE_CACHEABILITY(2)
#define LE_3_WB			LE_CACHEABILITY(3)

/* Target cache */
#define LE_TC_0_PAGETABLE	LE_TGT_CACHE(0)
#define LE_TC_1_LLC		LE_TGT_CACHE(1)
#define LE_TC_2_LLC_ELLC	LE_TGT_CACHE(2)
#define LE_TC_3_LLC_ELLC_ALT	LE_TGT_CACHE(3)

/* L3 caching options */
#define L3_0_DIRECT		L3_CACHEABILITY(0)
#define L3_1_UC			L3_CACHEABILITY(1)
#define L3_2_RESERVED		L3_CACHEABILITY(2)
#define L3_3_WB			L3_CACHEABILITY(3)

/* L4 caching options */
#define L4_0_WB                 REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 0)
#define L4_1_WT                 REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 1)
#define L4_3_UC                 REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 3)

#define XE2_L3_0_WB		REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 0)
/* XD: WB Transient Display */
#define XE2_L3_1_XD		REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 1)
#define XE2_L3_3_UC		REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 3)

#define XE2_L3_CLOS_MASK	REG_GENMASK(7, 6)

#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
	[__idx] = { \
		.control_value = __control_value, \
		.l3cc_value = __l3cc_value, \
		.used = 1, \
	}

/*
 * MOCS tables
 *
 * These are the MOCS tables that are programmed across all the rings.
 * The control value is programmed to all the rings that support the
 * MOCS registers. While the l3cc_values are only programmed to the
 * LNCFCMOCS0 - LNCFCMOCS32 registers.

Annotation

Implementation Notes