drivers/gpu/drm/xe/xe_nvm.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_nvm.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/xe_nvm.c
Extension
.c
Size
4389 bytes
Lines
179
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright(c) 2019-2025, Intel Corporation. All rights reserved.
 */

#include <linux/intel_dg_nvm_aux.h>
#include <linux/pci.h>

#include "xe_device.h"
#include "xe_mmio.h"
#include "xe_nvm.h"
#include "xe_pcode_api.h"
#include "regs/xe_gsc_regs.h"
#include "xe_sriov.h"

#define GEN12_GUNIT_NVM_BASE 0x00102040
#define GEN12_DEBUG_NVM_BASE 0x00101018

#define GEN12_CNTL_PROTECTED_NVM_REG 0x0010100C

#define GEN12_GUNIT_NVM_SIZE 0x80
#define GEN12_DEBUG_NVM_SIZE 0x4

#define NVM_NON_POSTED_ERASE_CHICKEN_BIT BIT(13)

#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3)

static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = {
	[0] = { .name = "DESCRIPTOR", },
	[2] = { .name = "GSC", },
	[9] = { .name = "PADDING", },
	[11] = { .name = "OptionROM", },
	[12] = { .name = "DAM", },
};

static void xe_nvm_release_dev(struct device *dev)
{
	struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
	struct intel_dg_nvm_dev *nvm = container_of(aux, struct intel_dg_nvm_dev, aux_dev);

	kfree(nvm);
}

static bool xe_nvm_non_posted_erase(struct xe_device *xe)
{
	struct xe_mmio *mmio = xe_root_tile_mmio(xe);

	switch (xe->info.platform) {
	case XE_CRESCENTISLAND:
	case XE_BATTLEMAGE:
		return !(xe_mmio_read32(mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) &
			 NVM_NON_POSTED_ERASE_CHICKEN_BIT);
	default:
		return false;
	}
}

static bool xe_nvm_writable_override(struct xe_device *xe)
{
	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
	bool writable_override;
	struct xe_reg reg;
	u32 test_bit;

	switch (xe->info.platform) {
	case XE_CRESCENTISLAND:
		reg = PCODE_SCRATCH(0);
		test_bit = FDO_MODE;
		break;
	case XE_BATTLEMAGE:
		reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE);
		test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
		break;
	case XE_PVC:
		reg = HECI_FWSTS2(PVC_GSC_HECI2_BASE);
		test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
		break;
	case XE_DG2:
		reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE);
		test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
		break;
	case XE_DG1:
		reg = HECI_FWSTS2(DG1_GSC_HECI2_BASE);
		test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
		break;
	default:
		drm_err(&xe->drm, "Unknown platform\n");
		return true;
	}

Annotation

Implementation Notes