drivers/gpu/drm/xe/xe_pat.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_pat.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_pat.c- Extension
.c- Size
- 23919 bytes
- Lines
- 754
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
xe_pat.huapi/drm/xe_drm.hgenerated/xe_wa_oob.hregs/xe_gt_regs.hregs/xe_reg_defs.hxe_assert.hxe_device.hxe_force_wake.hxe_gt.hxe_gt_mcr.hxe_mmio.hxe_sriov.hxe_wa.h
Detected Declarations
struct xe_pat_opsfunction xe_pat_index_labelfunction xelp_pat_entry_dumpfunction xehpc_pat_entry_dumpfunction xelpg_pat_entry_dumpfunction xe_pat_index_get_coh_modefunction xe_pat_index_get_comp_enfunction xe_pat_index_get_l3_policyfunction program_patfunction program_pat_mcrfunction xelp_dumpfunction xehp_dumpfunction xehpc_dumpfunction xelpg_dumpfunction xe2_pat_entry_dumpfunction xe3p_xpc_pat_entry_dumpfunction xe2_dumpfunction xe_pat_init_earlyfunction xe_pat_initfunction xe_pat_dumpfunction xe_pat_dump_sw_config
Annotated Snippet
struct xe_pat_ops {
void (*program_graphics)(struct xe_gt *gt, const struct xe_pat_table_entry table[],
int n_entries);
void (*program_media)(struct xe_gt *gt, const struct xe_pat_table_entry table[],
int n_entries);
int (*dump)(struct xe_gt *gt, struct drm_printer *p);
void (*entry_dump)(struct drm_printer *p, const char *label, u32 pat, bool rsvd);
};
static const struct xe_pat_table_entry xelp_pat_table[] = {
[0] = { XELP_PAT_WB, XE_COH_1WAY },
[1] = { XELP_PAT_WC, XE_COH_NONE },
[2] = { XELP_PAT_WT, XE_COH_NONE },
[3] = { XELP_PAT_UC, XE_COH_NONE },
};
static const struct xe_pat_table_entry xehpc_pat_table[] = {
[0] = { XELP_PAT_UC, XE_COH_NONE },
[1] = { XELP_PAT_WC, XE_COH_NONE },
[2] = { XELP_PAT_WT, XE_COH_NONE },
[3] = { XELP_PAT_WB, XE_COH_1WAY },
[4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE },
[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_1WAY },
[6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE },
[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_1WAY },
};
static const struct xe_pat_table_entry xelpg_pat_table[] = {
[0] = { XELPG_PAT_0_WB, XE_COH_NONE },
[1] = { XELPG_PAT_1_WT, XE_COH_NONE },
[2] = { XELPG_PAT_3_UC, XE_COH_NONE },
[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_1WAY },
[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_2WAY },
};
/*
* The Xe2 table is getting large/complicated so it's easier to review if
* provided in a form that exactly matches the bspec's formatting. The meaning
* of the fields here are:
* - no_promote: 0=promotable, 1=no promote
* - comp_en: 0=disable, 1=enable
* - l3clos: L3 class of service (0-3)
* - l3_policy: 0=WB, 1=XD ("WB - Transient Display"),
* 2=XA ("WB - Transient App" for Xe3p), 3=UC
* - l4_policy: 0=WB, 1=WT, 3=UC
* - coh_mode: 0=no snoop, 2=1-way coherent, 3=2-way coherent
*
* Reserved entries should be programmed with the maximum caching, minimum
* coherency (which matches an all-0's encoding), so we can just omit them
* in the table.
*
* Note: There is an implicit assumption in the driver that compression and
* coh_1way+ are mutually exclusive for platforms prior to Xe3. Starting
* with Xe3, compression can be combined with coherency. If using compression
* with coherency, userptr and imported dma-buf from external device will
* have uncleared ccs state. See also xe_bo_needs_ccs_pages().
*/
#define XE2_PAT(no_promote, comp_en, l3clos, l3_policy, l4_policy, __coh_mode) \
{ \
.value = (no_promote ? XE2_NO_PROMOTE : 0) | \
(comp_en ? XE2_COMP_EN : 0) | \
REG_FIELD_PREP(XE2_L3_CLOS, l3clos) | \
REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \
REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \
REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \
.coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE, \
.valid = 1 \
}
static const struct xe_pat_table_entry xe2_pat_table[] = {
[ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
[ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
[ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
[ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
[ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
[ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
[ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
[ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
[ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
[ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
[10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),
[11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),
[12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),
[13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),
[14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),
[15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),
/* 16..19 are reserved; leave set to all 0's */
[20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),
[21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),
[22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),
Annotation
- Immediate include surface: `xe_pat.h`, `uapi/drm/xe_drm.h`, `generated/xe_wa_oob.h`, `regs/xe_gt_regs.h`, `regs/xe_reg_defs.h`, `xe_assert.h`, `xe_device.h`, `xe_force_wake.h`.
- Detected declarations: `struct xe_pat_ops`, `function xe_pat_index_label`, `function xelp_pat_entry_dump`, `function xehpc_pat_entry_dump`, `function xelpg_pat_entry_dump`, `function xe_pat_index_get_coh_mode`, `function xe_pat_index_get_comp_en`, `function xe_pat_index_get_l3_policy`, `function program_pat`, `function program_pat_mcr`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.