drivers/gpu/drm/xe/xe_reg_whitelist.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_reg_whitelist.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xe/xe_reg_whitelist.c- Extension
.c- Size
- 8684 bytes
- Lines
- 280
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
xe_reg_whitelist.hregs/xe_engine_regs.hregs/xe_gt_regs.hregs/xe_oa_regs.hxe_device.hxe_gt.hxe_gt_types.hxe_gt_printk.hxe_platform_types.hxe_reg_sr.hxe_rtp.hxe_step.h
Detected Declarations
function match_not_renderfunction match_has_mertfunction match_multi_queue_classfunction XE_RTP_RULESfunction whitelist_apply_to_hwefunction xe_reg_whitelist_process_enginefunction xe_reg_whitelist_print_entryfunction xe_reg_whitelist_dump
Annotated Snippet
if (slot == RING_MAX_NONPRIV_SLOTS) {
xe_gt_err(hwe->gt,
"hwe %s: maximum register whitelist slots (%d) reached, refusing to add more\n",
hwe->name, RING_MAX_NONPRIV_SLOTS);
break;
}
xe_reg_whitelist_print_entry(&p, 0, reg, entry);
xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt);
slot++;
}
}
/**
* xe_reg_whitelist_process_engine - process table of registers to whitelist
* @hwe: engine instance to process whitelist for
*
* Process wwhitelist table for this platform, saving in @hwe all the
* registers that need to be whitelisted by the hardware so they can be accessed
* by userspace.
*/
void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
{
struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
&hwe->reg_whitelist, false);
whitelist_apply_to_hwe(hwe);
}
/**
* xe_reg_whitelist_print_entry - print one whitelist entry
* @p: DRM printer
* @indent: indent level
* @reg: register allowed/denied
* @entry: save-restore entry
*
* Print details about the entry added to allow/deny access
*/
void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
u32 reg, struct xe_reg_sr_entry *entry)
{
u32 val = entry->set_bits;
const char *access_str = "(invalid)";
unsigned int range_bit = 2;
u32 range_start, range_end;
bool deny;
deny = val & RING_FORCE_TO_NONPRIV_DENY;
switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) {
case RING_FORCE_TO_NONPRIV_RANGE_4:
range_bit = 4;
break;
case RING_FORCE_TO_NONPRIV_RANGE_16:
range_bit = 6;
break;
case RING_FORCE_TO_NONPRIV_RANGE_64:
range_bit = 8;
break;
}
range_start = reg & REG_GENMASK(25, range_bit);
range_end = range_start | REG_GENMASK(range_bit - 1, 0);
switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) {
case RING_FORCE_TO_NONPRIV_ACCESS_RW:
access_str = "rw";
break;
case RING_FORCE_TO_NONPRIV_ACCESS_RD:
access_str = "read";
break;
case RING_FORCE_TO_NONPRIV_ACCESS_WR:
access_str = "write";
break;
}
drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n",
range_start, range_end,
deny ? "deny" : "allow",
access_str);
}
/**
* xe_reg_whitelist_dump - print all whitelist entries
* @sr: Save/restore entries
* @p: DRM printer
*/
void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p)
Annotation
- Immediate include surface: `xe_reg_whitelist.h`, `regs/xe_engine_regs.h`, `regs/xe_gt_regs.h`, `regs/xe_oa_regs.h`, `xe_device.h`, `xe_gt.h`, `xe_gt_types.h`, `xe_gt_printk.h`.
- Detected declarations: `function match_not_render`, `function match_has_mert`, `function match_multi_queue_class`, `function XE_RTP_RULES`, `function whitelist_apply_to_hwe`, `function xe_reg_whitelist_process_engine`, `function xe_reg_whitelist_print_entry`, `function xe_reg_whitelist_dump`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.