drivers/gpu/drm/xe/xe_ring_ops.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xe/xe_ring_ops.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xe/xe_ring_ops.c
Extension
.c
Size
17171 bytes
Lines
653
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2022 Intel Corporation
 */

#include "xe_ring_ops.h"

#include <generated/xe_wa_oob.h>

#include "instructions/xe_gpu_commands.h"
#include "instructions/xe_mi_commands.h"
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
#include "xe_exec_queue.h"
#include "xe_gt_types.h"
#include "xe_lrc.h"
#include "xe_sched_job.h"
#include "xe_sriov.h"
#include "xe_vm_types.h"
#include "xe_vm.h"
#include "xe_wa.h"

/*
 * 3D-related flags that can't be set on _engines_ that lack access to the 3D
 * pipeline (i.e., CCS engines).
 */
#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
		PIPE_CONTROL_TILE_CACHE_FLUSH | \
		PIPE_CONTROL_DEPTH_STALL | \
		PIPE_CONTROL_STALL_AT_SCOREBOARD | \
		PIPE_CONTROL_PSD_SYNC | \
		PIPE_CONTROL_AMFS_FLUSH | \
		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)

/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
		PIPE_CONTROL_3D_ENGINE_FLAGS | \
		PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
		PIPE_CONTROL_FLUSH_ENABLE | \
		PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
		PIPE_CONTROL_DC_FLUSH_ENABLE)

static u32 preparser_disable(bool state)
{
	return MI_ARB_CHECK | BIT(8) | state;
}

static u32 *
__emit_aux_table_inv(u32 *cmd, const struct xe_reg reg, u32 adj_offset)
{
	*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) |
		 MI_LRI_MMIO_REMAP_EN;
	*cmd++ = reg.addr + adj_offset;
	*cmd++ = AUX_INV;
	*cmd++ = MI_SEMAPHORE_WAIT_TOKEN | MI_SEMAPHORE_REGISTER_POLL |
		 MI_SEMAPHORE_POLL | MI_SEMAPHORE_SAD_EQ_SDD;
	*cmd++ = 0;
	*cmd++ = reg.addr + adj_offset;
	*cmd++ = 0;
	*cmd++ = 0;

	return cmd;
}

static u32 *emit_aux_table_inv_render_compute(struct xe_gt *gt, u32 *cmd)
{
	return __emit_aux_table_inv(cmd, CCS_AUX_INV, gt->mmio.adj_offset);
}

static u32 *emit_aux_table_inv_video_decode(struct xe_gt *gt, u32 *cmd)
{
	return __emit_aux_table_inv(cmd, VD0_AUX_INV, gt->mmio.adj_offset);
}

static u32 *emit_aux_table_inv_video_enhance(struct xe_gt *gt, u32 *cmd)
{
	return __emit_aux_table_inv(cmd, VE0_AUX_INV, gt->mmio.adj_offset);
}

static int emit_aux_table_inv(struct xe_hw_engine *hwe, u32 *dw, int i)
{
	struct xe_gt *gt = hwe->gt;
	u32 *(*emit)(struct xe_gt *gt, u32 *cmd) =
		gt->ring_ops[hwe->class]->emit_aux_table_inv;

	if (emit)
		return emit(gt, dw + i) - dw;

Annotation

Implementation Notes