drivers/gpu/drm/xlnx/zynqmp_disp_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/xlnx/zynqmp_disp_regs.h
Extension
.h
Size
9559 bytes
Lines
197
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ZYNQMP_DISP_REGS_H_
#define _ZYNQMP_DISP_REGS_H_

#include <linux/bits.h>

/* Blender registers */
#define ZYNQMP_DISP_V_BLEND_BG_CLR_0			0x0
#define ZYNQMP_DISP_V_BLEND_BG_CLR_1			0x4
#define ZYNQMP_DISP_V_BLEND_BG_CLR_2			0x8
#define ZYNQMP_DISP_V_BLEND_BG_MAX			0xfff
#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA		0xc
#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(n)	((n) << 1)
#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN		BIT(0)
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT		0x14
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB		0x0
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444	0x1
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422	0x2
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY	0x3
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC	0x4
#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE	BIT(4)
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(n)		(0x18 + ((n) * 4))
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US		BIT(0)
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB		BIT(1)
#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS	BIT(8)
#define ZYNQMP_DISP_V_BLEND_NUM_COEFF			9
#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET			3
#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(n)		(0x20 + ((n) * 4))
#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(n)		(0x44 + ((n) * 4))
#define ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(n)		(0x68 + ((n) * 4))
#define ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(n)		(0x74 + ((n) * 4))
#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(n)		(0x80 + ((n) * 4))
#define ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(n)		(0xa4 + ((n) * 4))
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_ENABLE		0x1d0
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP1		0x1d4
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP2		0x1d8
#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP3		0x1dc

/* AV buffer manager registers */
#define ZYNQMP_DISP_AV_BUF_FMT				0x0
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_SHIFT		0
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK		(0x1f << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_UYVY		(0 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY		(1 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YVYU		(2 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV		(3 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16		(4 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24		(5 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI		(6 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO		(7 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2		(8 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444		(9 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888		(10 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880		(11 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10		(12 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10		(13 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_10	(14 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10		(15 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_10		(16 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10		(17 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10		(18 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420		(19 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420	(20 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420	(21 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420_10	(22 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10	(23 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420_10	(24 << 0)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_SHIFT		8
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK		(0xf << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888		(0 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888		(1 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888		(2 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888		(3 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551		(4 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444		(5 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565		(6 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_8BPP		(7 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_4BPP		(8 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_2BPP		(9 << 8)
#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_1BPP		(10 << 8)
#define ZYNQMP_DISP_AV_BUF_NON_LIVE_LATENCY		0x8
#define ZYNQMP_DISP_AV_BUF_CHBUF(n)			(0x10 + ((n) * 4))
#define ZYNQMP_DISP_AV_BUF_CHBUF_EN			BIT(0)
#define ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH			BIT(1)
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT	2
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MASK		(0xf << 2)
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX		0xf
#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX	0x3
#define ZYNQMP_DISP_AV_BUF_STATUS			0x28
#define ZYNQMP_DISP_AV_BUF_STC_CTRL			0x2c
#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EN			BIT(0)

Annotation

Implementation Notes