drivers/gpu/drm/xlnx/zynqmp_kms.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/xlnx/zynqmp_kms.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/xlnx/zynqmp_kms.c- Extension
.c- Size
- 15339 bytes
- Lines
- 543
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
drm/clients/drm_client_setup.hdrm/drm_atomic.hdrm/drm_atomic_helper.hdrm/drm_blend.hdrm/drm_bridge.hdrm/drm_bridge_connector.hdrm/drm_connector.hdrm/drm_crtc.hdrm/drm_device.hdrm/drm_drv.hdrm/drm_dumb_buffers.hdrm/drm_encoder.hdrm/drm_fbdev_dma.hdrm/drm_fourcc.hdrm/drm_framebuffer.hdrm/drm_gem_dma_helper.hdrm/drm_gem_framebuffer_helper.hdrm/drm_managed.hdrm/drm_mode_config.hdrm/drm_plane.hdrm/drm_probe_helper.hdrm/drm_simple_kms_helper.hdrm/drm_vblank.hlinux/clk.hlinux/delay.hlinux/pm_runtime.hlinux/spinlock.hzynqmp_disp.hzynqmp_dp.hzynqmp_dpsub.hzynqmp_kms.h
Detected Declarations
function Copyrightfunction zynqmp_dpsub_plane_atomic_checkfunction zynqmp_dpsub_plane_atomic_disablefunction zynqmp_dpsub_plane_atomic_updatefunction changedfunction zynqmp_dpsub_create_planesfunction zynqmp_dpsub_crtc_atomic_enablefunction zynqmp_dpsub_crtc_atomic_disablefunction zynqmp_dpsub_crtc_atomic_checkfunction zynqmp_dpsub_crtc_atomic_beginfunction zynqmp_dpsub_crtc_atomic_flushfunction zynqmp_dpsub_crtc_enable_vblankfunction zynqmp_dpsub_crtc_disable_vblankfunction zynqmp_dpsub_create_crtcfunction zynqmp_dpsub_map_crtc_to_planefunction zynqmp_dpsub_drm_handle_vblankfunction zynqmp_dpsub_dumb_createfunction zynqmp_dpsub_fb_createfunction zynqmp_dpsub_kms_initfunction zynqmp_dpsub_drm_releasefunction zynqmp_dpsub_drm_initfunction zynqmp_dpsub_drm_cleanup
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* ZynqMP DisplayPort Subsystem - KMS API
*
* Copyright (C) 2017 - 2021 Xilinx, Inc.
*
* Authors:
* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#include <drm/clients/drm_client_setup.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_blend.h>
#include <drm/drm_bridge.h>
#include <drm/drm_bridge_connector.h>
#include <drm/drm_connector.h>
#include <drm/drm_crtc.h>
#include <drm/drm_device.h>
#include <drm/drm_drv.h>
#include <drm/drm_dumb_buffers.h>
#include <drm/drm_encoder.h>
#include <drm/drm_fbdev_dma.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_managed.h>
#include <drm/drm_mode_config.h>
#include <drm/drm_plane.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>
#include <drm/drm_vblank.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include "zynqmp_disp.h"
#include "zynqmp_dp.h"
#include "zynqmp_dpsub.h"
#include "zynqmp_kms.h"
static inline struct zynqmp_dpsub *to_zynqmp_dpsub(struct drm_device *drm)
{
return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub;
}
/* -----------------------------------------------------------------------------
* DRM Planes
*/
static int zynqmp_dpsub_plane_atomic_check(struct drm_plane *plane,
struct drm_atomic_commit *state)
{
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
plane);
struct drm_crtc_state *crtc_state;
if (!new_plane_state->crtc)
return 0;
crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
return drm_atomic_helper_check_plane_state(new_plane_state,
crtc_state,
DRM_PLANE_NO_SCALING,
DRM_PLANE_NO_SCALING,
false, false);
}
static void zynqmp_dpsub_plane_atomic_disable(struct drm_plane *plane,
struct drm_atomic_commit *state)
{
struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
plane);
struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(plane->dev);
struct zynqmp_disp_layer *layer = dpsub->layers[plane->index];
if (!old_state->fb)
return;
zynqmp_disp_layer_disable(layer);
if (plane->index == ZYNQMP_DPSUB_LAYER_GFX)
zynqmp_disp_blend_set_global_alpha(dpsub->disp, false,
Annotation
- Immediate include surface: `drm/clients/drm_client_setup.h`, `drm/drm_atomic.h`, `drm/drm_atomic_helper.h`, `drm/drm_blend.h`, `drm/drm_bridge.h`, `drm/drm_bridge_connector.h`, `drm/drm_connector.h`, `drm/drm_crtc.h`.
- Detected declarations: `function Copyright`, `function zynqmp_dpsub_plane_atomic_check`, `function zynqmp_dpsub_plane_atomic_disable`, `function zynqmp_dpsub_plane_atomic_update`, `function changed`, `function zynqmp_dpsub_create_planes`, `function zynqmp_dpsub_crtc_atomic_enable`, `function zynqmp_dpsub_crtc_atomic_disable`, `function zynqmp_dpsub_crtc_atomic_check`, `function zynqmp_dpsub_crtc_atomic_begin`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.