drivers/gpu/host1x/dev.h
Source file repositories/reference/linux-study-clean/drivers/gpu/host1x/dev.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/host1x/dev.h- Extension
.h- Size
- 9954 bytes
- Lines
- 363
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/device.hlinux/iommu.hlinux/iova.hlinux/irqreturn.hlinux/platform_device.hlinux/reset.hcdma.hchannel.hcontext.hintr.hjob.hsyncpt.h
Detected Declarations
struct host1x_syncptstruct host1x_syncpt_basestruct host1x_channelstruct host1x_cdmastruct host1x_jobstruct push_bufferstruct outputstruct dentrystruct host1x_channel_opsstruct host1x_cdma_opsstruct host1x_pushbuffer_opsstruct host1x_debug_opsstruct host1x_syncpt_opsstruct host1x_intr_opsstruct host1x_sid_entrystruct host1x_table_descstruct host1x_infostruct host1xfunction host1x_hw_syncpt_restorefunction host1x_hw_syncpt_restore_wait_basefunction host1x_hw_syncpt_load_wait_basefunction host1x_hw_syncpt_loadfunction host1x_hw_syncpt_cpu_incrfunction host1x_hw_syncpt_assign_to_channelfunction host1x_hw_syncpt_enable_protectionfunction host1x_hw_intr_init_host_syncfunction host1x_hw_intr_set_syncpt_thresholdfunction host1x_hw_intr_enable_syncpt_intrfunction host1x_hw_intr_disable_syncpt_intrfunction host1x_hw_intr_disable_all_syncpt_intrsfunction host1x_hw_intr_free_syncpt_irqfunction host1x_hw_channel_initfunction host1x_hw_channel_submitfunction host1x_hw_cdma_startfunction host1x_hw_cdma_stopfunction host1x_hw_cdma_flushfunction host1x_hw_cdma_timeout_initfunction host1x_hw_cdma_timeout_destroyfunction host1x_hw_cdma_freezefunction host1x_hw_cdma_resumefunction host1x_hw_cdma_timeout_cpu_incrfunction host1x_hw_pushbuffer_initfunction host1x_hw_debug_initfunction host1x_hw_show_channel_cdmafunction host1x_hw_show_channel_fifofunction host1x_hw_show_mlocks
Annotated Snippet
struct host1x_channel_ops {
int (*init)(struct host1x_channel *channel, struct host1x *host,
unsigned int id);
int (*submit)(struct host1x_job *job);
};
struct host1x_cdma_ops {
void (*start)(struct host1x_cdma *cdma);
void (*stop)(struct host1x_cdma *cdma);
void (*flush)(struct host1x_cdma *cdma);
int (*timeout_init)(struct host1x_cdma *cdma);
void (*timeout_destroy)(struct host1x_cdma *cdma);
void (*freeze)(struct host1x_cdma *cdma);
void (*resume)(struct host1x_cdma *cdma, u32 getptr);
void (*timeout_cpu_incr)(struct host1x_cdma *cdma, u32 getptr,
u32 syncpt_incrs, u32 syncval, u32 nr_slots);
};
struct host1x_pushbuffer_ops {
void (*init)(struct push_buffer *pb);
};
struct host1x_debug_ops {
void (*debug_init)(struct dentry *de);
void (*show_channel_cdma)(struct host1x *host,
struct host1x_channel *ch,
struct output *o);
void (*show_channel_fifo)(struct host1x *host,
struct host1x_channel *ch,
struct output *o);
void (*show_mlocks)(struct host1x *host, struct output *output);
};
struct host1x_syncpt_ops {
void (*restore)(struct host1x_syncpt *syncpt);
void (*restore_wait_base)(struct host1x_syncpt *syncpt);
void (*load_wait_base)(struct host1x_syncpt *syncpt);
u32 (*load)(struct host1x_syncpt *syncpt);
int (*cpu_incr)(struct host1x_syncpt *syncpt);
void (*assign_to_channel)(struct host1x_syncpt *syncpt,
struct host1x_channel *channel);
void (*enable_protection)(struct host1x *host);
};
struct host1x_intr_ops {
int (*init_host_sync)(struct host1x *host, u32 cpm);
void (*set_syncpt_threshold)(
struct host1x *host, unsigned int id, u32 thresh);
void (*enable_syncpt_intr)(struct host1x *host, unsigned int id);
void (*disable_syncpt_intr)(struct host1x *host, unsigned int id);
void (*disable_all_syncpt_intrs)(struct host1x *host);
int (*free_syncpt_irq)(struct host1x *host);
irqreturn_t (*isr)(int irq, void *dev_id);
};
struct host1x_sid_entry {
unsigned int base;
unsigned int offset;
unsigned int limit;
};
struct host1x_table_desc {
unsigned int base;
unsigned int count;
};
struct host1x_info {
unsigned int nb_channels; /* host1x: number of channels supported */
unsigned int nb_pts; /* host1x: number of syncpoints supported */
unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
unsigned int nb_mlocks; /* host1x: number of mlocks supported */
int (*init)(struct host1x *host1x); /* initialize per SoC ops */
unsigned int sync_offset; /* offset of syncpoint registers */
u64 dma_mask; /* mask of addressable memory */
bool has_wide_gather; /* supports GATHER_W opcode */
bool has_hypervisor; /* has hypervisor registers */
bool has_common; /* has common registers separate from hypervisor */
unsigned int num_sid_entries;
const struct host1x_sid_entry *sid_table;
struct host1x_table_desc streamid_vm_table;
struct host1x_table_desc classid_vm_table;
struct host1x_table_desc mmio_vm_table;
/*
* On T20-T148, the boot chain may setup DC to increment syncpoints
* 26/27 on VBLANK. As such we cannot use these syncpoints until
* the display driver disables VBLANK increments.
*/
bool reserve_vblank_syncpts;
/*
Annotation
- Immediate include surface: `linux/device.h`, `linux/iommu.h`, `linux/iova.h`, `linux/irqreturn.h`, `linux/platform_device.h`, `linux/reset.h`, `cdma.h`, `channel.h`.
- Detected declarations: `struct host1x_syncpt`, `struct host1x_syncpt_base`, `struct host1x_channel`, `struct host1x_cdma`, `struct host1x_job`, `struct push_buffer`, `struct output`, `struct dentry`, `struct host1x_channel_ops`, `struct host1x_cdma_ops`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.