drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

Source file repositories/reference/linux-study-clean/drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h
Extension
.h
Size
7062 bytes
Lines
221
Domain
Driver Families
Bucket
drivers/hid
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ISHTP_ISH_REGS_H_
#define _ISHTP_ISH_REGS_H_


/*** IPC PCI Offsets and sizes ***/
/* ISH IPC Base Address */
#define IPC_REG_BASE		0x0000
/* Peripheral Interrupt Status Register */
#define IPC_REG_PISR_CHV_AB      (IPC_REG_BASE + 0x00)
/* Peripheral Interrupt Mask Register */
#define IPC_REG_PIMR_CHV_AB      (IPC_REG_BASE + 0x04)
/*BXT, CHV_K0*/
/*Peripheral Interrupt Status Register */
#define IPC_REG_PISR_BXT	 (IPC_REG_BASE + 0x0C)
/*Peripheral Interrupt Mask Register */
#define IPC_REG_PIMR_BXT	 (IPC_REG_BASE + 0x08)
/***********************************/
/* ISH Host Firmware status Register */
#define IPC_REG_ISH_HOST_FWSTS	(IPC_REG_BASE + 0x34)
/* Host Communication Register */
#define IPC_REG_HOST_COMM	(IPC_REG_BASE + 0x38)
/* Reset register */
#define IPC_REG_ISH_RST		(IPC_REG_BASE + 0x44)

/* Inbound doorbell register Host to ISH */
#define IPC_REG_HOST2ISH_DRBL	(IPC_REG_BASE + 0x48)
/* Outbound doorbell register ISH to Host */
#define IPC_REG_ISH2HOST_DRBL	(IPC_REG_BASE + 0x54)
/* ISH to HOST message registers */
#define IPC_REG_ISH2HOST_MSG	(IPC_REG_BASE + 0x60)
/* HOST to ISH message registers */
#define IPC_REG_HOST2ISH_MSG	(IPC_REG_BASE + 0xE0)
/* REMAP2 to enable DMA (D3 RCR) */
#define	IPC_REG_ISH_RMP2	(IPC_REG_BASE + 0x368)

#define	IPC_REG_MAX		(IPC_REG_BASE + 0x400)

/*** register bits - HISR ***/
/* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */
#define IPC_INT_HOST2ISH_BIT            (1<<0)
/***********************************/
/*CHV_A0, CHV_B0*/
/* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
#define IPC_INT_ISH2HOST_BIT_CHV_AB	(1<<3)
/*BXT, CHV_K0*/
/* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
#define IPC_INT_ISH2HOST_BIT_BXT	(1<<0)
/***********************************/

/* bit corresponds ISH2HOST busy clear interrupt in PIMR register */
#define IPC_INT_ISH2HOST_CLR_MASK_BIT	(1<<11)

/* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
#define IPC_INT_ISH2HOST_CLR_OFFS	(0)

/* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
#define IPC_INT_ISH2HOST_CLR_BIT	(1<<IPC_INT_ISH2HOST_CLR_OFFS)

/* bit corresponds busy bit in doorbell registers */
#define IPC_DRBL_BUSY_OFFS		(31)
#define IPC_DRBL_BUSY_BIT		(1<<IPC_DRBL_BUSY_OFFS)

#define	IPC_HOST_OWNS_MSG_OFFS		(30)

/*
 * A0: bit means that host owns MSGnn registers and is reading them.
 * ISH FW may not write to them
 */
#define	IPC_HOST_OWNS_MSG_BIT		(1<<IPC_HOST_OWNS_MSG_OFFS)

/*
 * Host status bits (HOSTCOMM)
 */
/* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
#define IPC_HOSTCOMM_READY_OFFS		(7)
#define IPC_HOSTCOMM_READY_BIT		(1<<IPC_HOSTCOMM_READY_OFFS)

/***********************************/
/*CHV_A0, CHV_B0*/
#define	IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB	(31)
#define	IPC_HOSTCOMM_INT_EN_BIT_CHV_AB		\
	(1<<IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB)
/*BXT, CHV_K0*/
#define IPC_PIMR_INT_EN_OFFS_BXT	(0)
#define IPC_PIMR_INT_EN_BIT_BXT		(1<<IPC_PIMR_INT_EN_OFFS_BXT)

#define IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT	(8)
#define IPC_HOST2ISH_BUSYCLEAR_MASK_BIT		\
	(1<<IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT)
/***********************************/

Annotation

Implementation Notes