drivers/hte/hte-tegra194.c

Source file repositories/reference/linux-study-clean/drivers/hte/hte-tegra194.c

File Facts

System
Linux kernel
Corpus path
drivers/hte/hte-tegra194.c
Extension
.c
Size
28221 bytes
Lines
996
Domain
Driver Families
Bucket
drivers/hte
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hte_slices {
	u32 r_val;
	unsigned long flags;
	/* to prevent lines mapped to same slice updating its register */
	spinlock_t s_lock;
};

struct tegra_hte_line_mapped {
	int slice;
	u32 bit_index;
};

struct tegra_hte_line_data {
	unsigned long flags;
	void *data;
};

struct tegra_hte_data {
	enum tegra_hte_type type;
	u32 slices;
	u32 map_sz;
	u32 sec_map_sz;
	u64 tsc_clkrate_hz;
	u32 tsc_clkrate_ns;
	const struct tegra_hte_line_mapped *map;
	const struct tegra_hte_line_mapped *sec_map;
};

struct tegra_hte_soc {
	int hte_irq;
	u32 itr_thrshld;
	u32 conf_rval;
	struct hte_slices *sl;
	const struct tegra_hte_data *prov_data;
	struct tegra_hte_line_data *line_data;
	struct hte_chip *chip;
	struct gpio_device *gdev;
	void __iomem *regs;
};

static const struct tegra_hte_line_mapped tegra194_aon_gpio_map[] = {
	/* gpio, slice, bit_index */
	/* AA port */
	[0]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
	[1]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
	[2]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
	[3]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
	[4]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
	[5]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
	[6]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
	[7]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
	/* BB port */
	[8]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
	[9]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
	[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
	[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
	/* CC port */
	[12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
	[13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
	[14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
	[15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
	[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
	[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
	[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
	[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
	/* DD port */
	[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
	[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
	[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
	/* EE port */
	[23] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29},
	[24] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28},
	[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
	[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
	[27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
	[28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
	[29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
};

static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = {
	/* gpio, slice, bit_index */
	/* AA port */
	[0]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
	[1]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
	[2]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
	[3]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
	[4]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
	[5]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
	[6]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
	[7]  = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},

Annotation

Implementation Notes