drivers/hwmon/ltc4222.c
Source file repositories/reference/linux-study-clean/drivers/hwmon/ltc4222.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/hwmon/ltc4222.c- Extension
.c- Size
- 6201 bytes
- Lines
- 222
- Domain
- Driver Families
- Bucket
- drivers/hwmon
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/err.hlinux/slab.hlinux/bitops.hlinux/i2c.hlinux/hwmon.hlinux/hwmon-sysfs.hlinux/jiffies.hlinux/regmap.h
Detected Declarations
function Copyrightfunction ltc4222_value_showfunction ltc4222_bool_showfunction ltc4222_probe
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Linear Technology LTC4222 Dual Hot Swap controller
*
* Copyright (c) 2014 Guenter Roeck
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
#include <linux/regmap.h>
/* chip registers */
#define LTC4222_CONTROL1 0xd0
#define LTC4222_ALERT1 0xd1
#define LTC4222_STATUS1 0xd2
#define LTC4222_FAULT1 0xd3
#define LTC4222_CONTROL2 0xd4
#define LTC4222_ALERT2 0xd5
#define LTC4222_STATUS2 0xd6
#define LTC4222_FAULT2 0xd7
#define LTC4222_SOURCE1 0xd8
#define LTC4222_SOURCE2 0xda
#define LTC4222_ADIN1 0xdc
#define LTC4222_ADIN2 0xde
#define LTC4222_SENSE1 0xe0
#define LTC4222_SENSE2 0xe2
#define LTC4222_ADC_CONTROL 0xe4
/*
* Fault register bits
*/
#define FAULT_OV BIT(0)
#define FAULT_UV BIT(1)
#define FAULT_OC BIT(2)
#define FAULT_POWER_BAD BIT(3)
#define FAULT_FET_BAD BIT(5)
/* Return the voltage from the given register in mV or mA */
static int ltc4222_get_value(struct device *dev, u8 reg)
{
struct regmap *regmap = dev_get_drvdata(dev);
unsigned int val;
u8 buf[2];
int ret;
ret = regmap_bulk_read(regmap, reg, buf, 2);
if (ret < 0)
return ret;
val = ((buf[0] << 8) + buf[1]) >> 6;
switch (reg) {
case LTC4222_ADIN1:
case LTC4222_ADIN2:
/* 1.25 mV resolution. Convert to mV. */
val = DIV_ROUND_CLOSEST(val * 5, 4);
break;
case LTC4222_SOURCE1:
case LTC4222_SOURCE2:
/* 31.25 mV resolution. Convert to mV. */
val = DIV_ROUND_CLOSEST(val * 125, 4);
break;
case LTC4222_SENSE1:
case LTC4222_SENSE2:
/*
* 62.5 uV resolution. Convert to current as measured with
* an 1 mOhm sense resistor, in mA. If a different sense
* resistor is installed, calculate the actual current by
* dividing the reported current by the sense resistor value
* in mOhm.
*/
val = DIV_ROUND_CLOSEST(val * 125, 2);
break;
default:
return -EINVAL;
}
return val;
}
static ssize_t ltc4222_value_show(struct device *dev,
struct device_attribute *da, char *buf)
{
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/err.h`, `linux/slab.h`, `linux/bitops.h`, `linux/i2c.h`, `linux/hwmon.h`, `linux/hwmon-sysfs.h`.
- Detected declarations: `function Copyright`, `function ltc4222_value_show`, `function ltc4222_bool_show`, `function ltc4222_probe`.
- Atlas domain: Driver Families / drivers/hwmon.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.