drivers/hwtracing/coresight/coresight-etm4x.h

Source file repositories/reference/linux-study-clean/drivers/hwtracing/coresight/coresight-etm4x.h

File Facts

System
Linux kernel
Corpus path
drivers/hwtracing/coresight/coresight-etm4x.h
Extension
.h
Size
37112 bytes
Lines
1116
Domain
Driver Families
Bucket
drivers/hwtracing
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct etmv4_config {
	u64				mode;
	u32				pe_sel;
	u32				cfg;
	u32				eventctrl0;
	u32				eventctrl1;
	u32				stall_ctrl;
	u32				ts_ctrl; /* TRCTSCTLR */
	u32				ccctlr;
	u32				bb_ctrl;
	u32				vinst_ctrl;
	u32				viiectlr;
	u32				vissctlr;
	u32				vipcssctlr;
	u8				seq_idx;
	u8				syncfreq;
	u32				seq_ctrl[ETM_MAX_SEQ_STATES];
	u32				seq_rst;
	u32				seq_state;
	u8				cntr_idx;
	u32				cntrldvr[ETMv4_MAX_CNTR]; /* TRCCNTRLDVRn */
	u32				cntr_ctrl[ETMv4_MAX_CNTR];  /* TRCCNTCTLRn */
	u32				cntr_val[ETMv4_MAX_CNTR]; /* TRCCNTVRn */
	u8				res_idx;
	u32				res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */
	u8				ss_idx;
	u32				ss_ctrl[ETM_MAX_SS_CMP];
	u32				ss_status[ETM_MAX_SS_CMP];
	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
	u8				addr_idx;
	u64				addr_val[ETM_MAX_SINGLE_ADDR_CMP];
	u64				addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
	u8				addr_type[ETM_MAX_SINGLE_ADDR_CMP];
	u8				ctxid_idx;
	u64				ctxid_pid[ETMv4_MAX_CTXID_CMP];
	u32				ctxid_mask0;
	u32				ctxid_mask1;
	u8				vmid_idx;
	u64				vmid_val[ETM_MAX_VMID_CMP];
	u32				vmid_mask0;
	u32				vmid_mask1;
	u32				ext_inp;
	u8				s_ex_level;
};

/**
 * struct etm4_save_state - state to be preserved when ETM is without power
 */
struct etmv4_save_state {
	u32	trcprocselr;
	u32	trcconfigr;
	u32	trcauxctlr;
	u32	trceventctl0r;
	u32	trceventctl1r;
	u32	trcstallctlr;
	u32	trctsctlr;
	u32	trcsyncpr;
	u32	trcccctlr;
	u32	trcbbctlr;
	u32	trctraceidr;
	u32	trcqctlr;

	u32	trcvictlr;
	u32	trcviiectlr;
	u32	trcvissctlr;
	u32	trcvipcssctlr;

	u32	trcseqevr[ETM_MAX_SEQ_STATES];
	u32	trcseqrstevr;
	u32	trcseqstr;
	u32	trcextinselr;
	u32	trccntrldvr[ETMv4_MAX_CNTR];
	u32	trccntctlr[ETMv4_MAX_CNTR];
	u32	trccntvr[ETMv4_MAX_CNTR];

	u32	trcrsctlr[ETM_MAX_RES_SEL];

	u32	trcssccr[ETM_MAX_SS_CMP];
	u32	trcsscsr[ETM_MAX_SS_CMP];
	u32	trcsspcicr[ETM_MAX_SS_CMP];

	u64	trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
	u64	trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
	u64	trccidcvr[ETMv4_MAX_CTXID_CMP];
	u64	trcvmidcvr[ETM_MAX_VMID_CMP];
	u32	trccidcctlr0;
	u32	trccidcctlr1;
	u32	trcvmidcctlr0;
	u32	trcvmidcctlr1;

Annotation

Implementation Notes