drivers/i2c/busses/i2c-qcom-cci.c

Source file repositories/reference/linux-study-clean/drivers/i2c/busses/i2c-qcom-cci.c

File Facts

System
Linux kernel
Corpus path
drivers/i2c/busses/i2c-qcom-cci.c
Extension
.c
Size
20425 bytes
Lines
855
Domain
Driver Families
Bucket
drivers/i2c
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hw_params {
	u16 thigh; /* HIGH period of the SCL clock in clock ticks */
	u16 tlow; /* LOW period of the SCL clock */
	u16 tsu_sto; /* set-up time for STOP condition */
	u16 tsu_sta; /* set-up time for a repeated START condition */
	u16 thd_dat; /* data hold time */
	u16 thd_sta; /* hold time (repeated) START condition */
	u16 tbuf; /* bus free time between a STOP and START condition */
	u8 scl_stretch_en;
	u16 trdhld;
	u16 tsp; /* pulse width of spikes suppressed by the input filter */
};

struct cci;

struct cci_master {
	struct i2c_adapter adap;
	u16 master;
	u8 mode;
	int status;
	struct completion irq_complete;
	struct cci *cci;
};

struct cci_data {
	unsigned int num_masters;
	struct i2c_adapter_quirks quirks;
	u16 queue_size[NUM_QUEUES];
	struct hw_params params[3];
};

struct cci {
	struct device *dev;
	void __iomem *base;
	unsigned int irq;
	const struct cci_data *data;
	struct clk_bulk_data *clocks;
	int nclocks;
	struct cci_master master[NUM_MASTERS];
};

static irqreturn_t cci_isr(int irq, void *dev)
{
	struct cci *cci = dev;
	u32 val, reset = 0;
	int ret = IRQ_NONE;

	val = readl(cci->base + CCI_IRQ_STATUS_0);
	writel(val, cci->base + CCI_IRQ_CLEAR_0);
	writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);

	if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) {
		complete(&cci->master[0].irq_complete);
		if (cci->master[1].master)
			complete(&cci->master[1].irq_complete);
		ret = IRQ_HANDLED;
	}

	if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE ||
			val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT ||
			val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) {
		cci->master[0].status = 0;
		complete(&cci->master[0].irq_complete);
		ret = IRQ_HANDLED;
	}

	if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE ||
			val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT ||
			val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) {
		cci->master[1].status = 0;
		complete(&cci->master[1].irq_complete);
		ret = IRQ_HANDLED;
	}

	if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) {
		reset = CCI_RESET_CMD_M0_MASK;
		ret = IRQ_HANDLED;
	}

	if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) {
		reset = CCI_RESET_CMD_M1_MASK;
		ret = IRQ_HANDLED;
	}

	if (unlikely(reset))
		writel(reset, cci->base + CCI_RESET_CMD);

	if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) {
		if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR ||
			val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR)

Annotation

Implementation Notes