drivers/i2c/busses/i2c-tegra.c

Source file repositories/reference/linux-study-clean/drivers/i2c/busses/i2c-tegra.c

File Facts

System: Linux kernel
Corpus path: drivers/i2c/busses/i2c-tegra.c
Extension: .c
Size: 72209 bytes
Lines: 2512
Domain: Driver Families
Bucket: drivers/i2c
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Touches IRQ or DMA behavior; this matters for the representative real-device path.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/acpi.h
linux/bitfield.h
linux/clk.h
linux/delay.h
linux/dmaengine.h
linux/dma-mapping.h
linux/err.h
linux/i2c.h
linux/init.h
linux/interrupt.h
linux/io.h
linux/iopoll.h
linux/irq.h
linux/kernel.h
linux/ktime.h
linux/module.h
linux/of.h
linux/pinctrl/consumer.h
linux/platform_device.h
linux/pm_runtime.h
linux/reset.h

Detected Declarations

struct tegra_i2c_regs
struct tegra_i2c_hw_feature
struct tegra_i2c_dev
enum msg_end_type
enum tegra_i2c_variant
function dvc_writel
function dvc_readl
function i2c_writel
function i2c_readl
function i2c_writesl
function i2c_writesl_vi
function i2c_readsl
function tegra_i2c_mutex_acquired
function tegra_i2c_mutex_trylock
function tegra_i2c_mutex_lock
function tegra_i2c_mutex_unlock
function tegra_i2c_mask_irq
function tegra_i2c_unmask_irq
function tegra_i2c_dma_complete
function tegra_i2c_dma_submit
function tegra_i2c_release_dma
function tegra_i2c_init_dma
function DVC
function tegra_i2c_vi_init
function tegra_i2c_poll_register
function tegra_i2c_flush_fifos
function tegra_i2c_wait_for_config_load
function tegra_i2c_master_reset
function tegra_i2c_init
function tegra_i2c_disable_packet_mode
function tegra_i2c_empty_rx_fifo
function tegra_i2c_fill_tx_fifo
function tegra_i2c_isr
function tegra_i2c_config_fifo_trig
function tegra_i2c_poll_completion
function tegra_i2c_wait_completion
function tegra_i2c_issue_bus_clear
function tegra_i2c_push_packet_header
function tegra_i2c_error_recover
function tegra_i2c_xfer_msg
function tegra_i2c_xfer
function tegra_i2c_xfer_atomic
function tegra_i2c_func
function tegra_i2c_parse_dt
function tegra_i2c_init_clocks
function tegra_i2c_release_clocks
function tegra_i2c_init_hardware
function tegra_i2c_probe

Annotated Snippet

struct tegra_i2c_regs {
	unsigned int cnfg;
	unsigned int status;
	unsigned int sl_cnfg;
	unsigned int sl_addr1;
	unsigned int sl_addr2;
	unsigned int tlow_sext;
	unsigned int tx_fifo;
	unsigned int rx_fifo;
	unsigned int packet_transfer_status;
	unsigned int fifo_control;
	unsigned int fifo_status;
	unsigned int int_mask;
	unsigned int int_status;
	unsigned int clk_divisor;
	unsigned int bus_clear_cnfg;
	unsigned int bus_clear_status;
	unsigned int config_load;
	unsigned int clken_override;
	unsigned int interface_timing_0;
	unsigned int interface_timing_1;
	unsigned int hs_interface_timing_0;
	unsigned int hs_interface_timing_1;
	unsigned int master_reset_cntrl;
	unsigned int mst_fifo_control;
	unsigned int mst_fifo_status;
	unsigned int fairness_arb;
	unsigned int sw_mutex;
};

static const struct tegra_i2c_regs tegra20_i2c_regs = {
	.cnfg = 0x000,
	.status = 0x01c,
	.sl_cnfg = 0x020,
	.sl_addr1 = 0x02c,
	.sl_addr2 = 0x030,
	.tx_fifo = 0x050,
	.rx_fifo = 0x054,
	.packet_transfer_status = 0x058,
	.fifo_control = 0x05c,
	.fifo_status = 0x060,
	.int_mask = 0x064,
	.int_status = 0x068,
	.clk_divisor = 0x06c,
	.bus_clear_cnfg = 0x084,
	.bus_clear_status = 0x088,
	.config_load = 0x08c,
	.clken_override = 0x090,
	.interface_timing_0 = 0x094,
	.interface_timing_1 = 0x098,
	.hs_interface_timing_0 = 0x09c,
	.hs_interface_timing_1 = 0x0a0,
	.master_reset_cntrl = 0x0a8,
	.mst_fifo_control = 0x0b4,
	.mst_fifo_status = 0x0b8,
};

#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
static const struct tegra_i2c_regs tegra20_dvc_i2c_regs = {
	.cnfg = 0x040,
	.status = 0x05c,
	.tx_fifo = 0x060,
	.rx_fifo = 0x064,
	.packet_transfer_status = 0x068,
	.fifo_control = 0x06c,
	.fifo_status = 0x070,
	.int_mask = 0x074,
	.int_status = 0x078,
	.clk_divisor = 0x07c,
	.bus_clear_cnfg = 0x094,
	.bus_clear_status = 0x098,
	.config_load = 0x09c,
	.clken_override = 0x0a0,
	.interface_timing_0 = 0x0a4,
	.interface_timing_1 = 0x0a8,
	.hs_interface_timing_0 = 0x0ac,
	.hs_interface_timing_1 = 0x0b0,
	.master_reset_cntrl = 0x0b8,
	.mst_fifo_control = 0x0c4,
	.mst_fifo_status = 0x0c8,
};
#endif

#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
static const struct tegra_i2c_regs tegra210_vi_i2c_regs = {
	.cnfg = 0x0c00,
	.status = 0x0c70,
	.tlow_sext = 0x0cd0,
	.tx_fifo = 0x0d40,
	.rx_fifo = 0x0d50,

Annotation

Immediate include surface: `linux/acpi.h`, `linux/bitfield.h`, `linux/clk.h`, `linux/delay.h`, `linux/dmaengine.h`, `linux/dma-mapping.h`, `linux/err.h`, `linux/i2c.h`.
Detected declarations: `struct tegra_i2c_regs`, `struct tegra_i2c_hw_feature`, `struct tegra_i2c_dev`, `enum msg_end_type`, `enum tegra_i2c_variant`, `function dvc_writel`, `function dvc_readl`, `function i2c_writel`, `function i2c_readl`, `function i2c_writesl`.
Atlas domain: Driver Families / drivers/i2c.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.