drivers/iio/accel/adxl372.c

Source file repositories/reference/linux-study-clean/drivers/iio/accel/adxl372.c

File Facts

System
Linux kernel
Corpus path
drivers/iio/accel/adxl372.c
Extension
.c
Size
36060 bytes
Lines
1336
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct adxl372_axis_lookup {
	unsigned int bits;
	enum adxl372_fifo_format fifo_format;
};

static const struct adxl372_axis_lookup adxl372_axis_lookup_table[] = {
	{ BIT(0), ADXL372_X_FIFO },
	{ BIT(1), ADXL372_Y_FIFO },
	{ BIT(2), ADXL372_Z_FIFO },
	{ BIT(0) | BIT(1), ADXL372_XY_FIFO },
	{ BIT(0) | BIT(2), ADXL372_XZ_FIFO },
	{ BIT(1) | BIT(2), ADXL372_YZ_FIFO },
	{ BIT(0) | BIT(1) | BIT(2), ADXL372_XYZ_FIFO },
};

static const struct iio_event_spec adxl372_events[] = {
	{
		.type = IIO_EV_TYPE_THRESH,
		.dir = IIO_EV_DIR_RISING,
		.mask_separate = BIT(IIO_EV_INFO_VALUE),
		.mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE),
	}, {
		.type = IIO_EV_TYPE_THRESH,
		.dir = IIO_EV_DIR_FALLING,
		.mask_separate = BIT(IIO_EV_INFO_VALUE),
		.mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD) | BIT(IIO_EV_INFO_ENABLE),
	},
};

#define ADXL372_ACCEL_CHANNEL(index, reg, axis) {			\
	.type = IIO_ACCEL,						\
	.address = reg,							\
	.modified = 1,							\
	.channel2 = IIO_MOD_##axis,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
	.info_mask_shared_by_type =					\
		BIT(IIO_CHAN_INFO_SCALE) |				\
		BIT(IIO_CHAN_INFO_SAMP_FREQ) |				\
		BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),	\
	.info_mask_shared_by_type_available =				\
		BIT(IIO_CHAN_INFO_SAMP_FREQ) |				\
		BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),	\
	.scan_index = index,						\
	.scan_type = {							\
		.sign = 's',						\
		.realbits = 12,						\
		.storagebits = 16,					\
		.shift = 4,						\
		.endianness = IIO_BE,					\
	},								\
	.event_spec = adxl372_events,					\
	.num_event_specs = ARRAY_SIZE(adxl372_events)			\
}

static const struct iio_chan_spec adxl372_channels[] = {
	ADXL372_ACCEL_CHANNEL(0, ADXL372_X_DATA_H, X),
	ADXL372_ACCEL_CHANNEL(1, ADXL372_Y_DATA_H, Y),
	ADXL372_ACCEL_CHANNEL(2, ADXL372_Z_DATA_H, Z),
};

struct adxl372_state {
	const struct adxl372_chip_info	*chip_info;
	int				irq;
	struct device			*dev;
	struct regmap			*regmap;
	struct iio_trigger		*dready_trig;
	struct iio_trigger		*peak_datardy_trig;
	enum adxl372_fifo_mode		fifo_mode;
	enum adxl372_fifo_format	fifo_format;
	unsigned int			fifo_axis_mask;
	enum adxl372_op_mode		op_mode;
	enum adxl372_act_proc_mode	act_proc_mode;
	enum adxl372_odr		odr;
	enum adxl372_bandwidth		bw;
	u32				act_time_ms;
	u32				inact_time_ms;
	u8				fifo_set_size;
	unsigned long			int1_bitmask;
	u16				watermark;
	__be16				fifo_buf[ADXL372_FIFO_SIZE];
	bool				peak_fifo_mode_en;
	struct mutex			threshold_m; /* lock for threshold */
};

static const unsigned long adxl372_channel_masks[] = {
	BIT(0), BIT(1), BIT(2),
	BIT(0) | BIT(1),
	BIT(0) | BIT(2),
	BIT(1) | BIT(2),
	BIT(0) | BIT(1) | BIT(2),

Annotation

Implementation Notes