drivers/iio/accel/bma180.c

Source file repositories/reference/linux-study-clean/drivers/iio/accel/bma180.c

File Facts

System
Linux kernel
Corpus path
drivers/iio/accel/bma180.c
Extension
.c
Size
29199 bytes
Lines
1138
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct bma180_part_info {
	u8 chip_id;
	const struct iio_chan_spec *channels;
	unsigned int num_channels;
	const int *scale_table;
	unsigned int num_scales;
	const int *bw_table;
	unsigned int num_bw;
	int temp_offset;

	u8 int_reset_reg, int_reset_mask;
	u8 sleep_reg, sleep_mask;
	u8 bw_reg, bw_mask, bw_offset;
	u8 scale_reg, scale_mask;
	u8 power_reg, power_mask, lowpower_val;
	u8 int_enable_reg, int_enable_mask;
	u8 softreset_reg, softreset_val;

	int (*chip_config)(struct bma180_data *data);
	void (*chip_disable)(struct bma180_data *data);
};

/* Register set */
#define BMA023_CTRL_REG0	0x0a
#define BMA023_CTRL_REG1	0x0b
#define BMA023_CTRL_REG2	0x14
#define BMA023_CTRL_REG3	0x15

#define BMA023_RANGE_MASK	GENMASK(4, 3) /* Range of accel values */
#define BMA023_BW_MASK		GENMASK(2, 0) /* Accel bandwidth */
#define BMA023_SLEEP		BIT(0)
#define BMA023_INT_RESET_MASK	BIT(6)
#define BMA023_NEW_DATA_INT	BIT(5) /* Intr every new accel data is ready */
#define BMA023_RESET_VAL	BIT(1)

#define BMA180_CHIP_ID		0x00 /* Need to distinguish BMA180 from other */
#define BMA180_ACC_X_LSB	0x02 /* First of 6 registers of accel data */
#define BMA180_TEMP		0x08
#define BMA180_CTRL_REG0	0x0d
#define BMA180_RESET		0x10
#define BMA180_BW_TCS		0x20
#define BMA180_CTRL_REG3	0x21
#define BMA180_TCO_Z		0x30
#define BMA180_OFFSET_LSB1	0x35

/* BMA180_CTRL_REG0 bits */
#define BMA180_DIS_WAKE_UP	BIT(0) /* Disable wake up mode */
#define BMA180_SLEEP		BIT(1) /* 1 - chip will sleep */
#define BMA180_EE_W		BIT(4) /* Unlock writing to addr from 0x20 */
#define BMA180_RESET_INT	BIT(6) /* Reset pending interrupts */

/* BMA180_CTRL_REG3 bits */
#define BMA180_NEW_DATA_INT	BIT(1) /* Intr every new accel data is ready */

/* BMA180_OFFSET_LSB1 skipping mode bit */
#define BMA180_SMP_SKIP		BIT(0)

/* Bit masks for registers bit fields */
#define BMA180_RANGE		0x0e /* Range of measured accel values */
#define BMA180_BW		0xf0 /* Accel bandwidth */
#define BMA180_MODE_CONFIG	0x03 /* Config operation modes */

/* We have to write this value in reset register to do soft reset */
#define BMA180_RESET_VAL	0xb6

#define BMA023_ID_REG_VAL	0x02
#define BMA180_ID_REG_VAL	0x03
#define BMA250_ID_REG_VAL	0x03

/* Chip power modes */
#define BMA180_LOW_POWER	0x03

#define BMA250_RANGE_REG	0x0f
#define BMA250_BW_REG		0x10
#define BMA250_POWER_REG	0x11
#define BMA250_RESET_REG	0x14
#define BMA250_INT_ENABLE_REG	0x17
#define BMA250_INT_MAP_REG	0x1a
#define BMA250_INT_RESET_REG	0x21

#define BMA250_RANGE_MASK	GENMASK(3, 0) /* Range of accel values */
#define BMA250_BW_MASK		GENMASK(4, 0) /* Accel bandwidth */
#define BMA250_BW_OFFSET	8
#define BMA250_SUSPEND_MASK	BIT(7) /* chip will sleep */
#define BMA250_LOWPOWER_MASK	BIT(6)
#define BMA250_DATA_INTEN_MASK	BIT(4)
#define BMA250_INT1_DATA_MASK	BIT(0)
#define BMA250_INT_RESET_MASK	BIT(7) /* Reset pending interrupts */

struct bma180_data {

Annotation

Implementation Notes