drivers/iio/accel/bma400.h

Source file repositories/reference/linux-study-clean/drivers/iio/accel/bma400.h

File Facts

System
Linux kernel
Corpus path
drivers/iio/accel/bma400.h
Extension
.h
Size
5920 bytes
Lines
193
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _BMA400_H_
#define _BMA400_H_

#include <linux/bits.h>
#include <linux/regmap.h>

/*
 * Read-Only Registers
 */

/* Chip ID of BMA 400 devices found in the chip ID register. */
#define BMA400_ID_REG_VAL           0x90

/* Status and ID registers */
#define BMA400_CHIP_ID_REG          0x00
#define BMA400_ERR_REG              0x02
#define BMA400_STATUS_REG           0x03

/* Acceleration registers */
#define BMA400_ACC_X_LSB_REG		0x04
#define BMA400_ACC_X_MSB_REG		0x05
#define BMA400_ACC_Y_LSB_REG		0x06
#define BMA400_ACC_Y_MSB_REG		0x07
#define BMA400_ACC_Z_LSB_REG		0x08
#define BMA400_ACC_Z_MSB_REG		0x09

/* Sensor time registers */
#define BMA400_SENSOR_TIME0_REG         0x0a
#define BMA400_SENSOR_TIME1_REG         0x0b
#define BMA400_SENSOR_TIME2_REG         0x0c

/* Event and interrupt registers */
#define BMA400_EVENT_REG            0x0d

#define BMA400_INT_STAT0_REG        0x0e
#define BMA400_INT_STAT0_GEN1_MASK		BIT(2)
#define BMA400_INT_STAT0_GEN2_MASK		BIT(3)
#define BMA400_INT_STAT0_DRDY_MASK		BIT(7)

#define BMA400_INT_STAT1_REG        0x0f
#define BMA400_INT_STAT1_STEP_INT_MASK		GENMASK(9, 8)
#define BMA400_INT_STAT1_S_TAP_MASK		BIT(10)
#define BMA400_INT_STAT1_D_TAP_MASK		BIT(11)

#define BMA400_INT_STAT2_REG        0x10

/* Bit present in all INT_STAT registers */
#define BMA400_INT_STAT_ENG_OVRRUN_MASK		BIT(4)

/* Temperature register */
#define BMA400_TEMP_DATA_REG        0x11

/* FIFO length and data registers */
#define BMA400_FIFO_LENGTH0_REG     0x12
#define BMA400_FIFO_LENGTH1_REG     0x13
#define BMA400_FIFO_DATA_REG        0x14

/* Step count registers */
#define BMA400_STEP_CNT0_REG        0x15
#define BMA400_STEP_CNT1_REG        0x16
#define BMA400_STEP_CNT3_REG        0x17
#define BMA400_STEP_STAT_REG        0x18
#define BMA400_STEP_RAW_LEN         0x03

/*
 * Read-write configuration registers
 */
#define BMA400_ACC_CONFIG0_REG		0x19
#define BMA400_ACC_CONFIG0_LP_OSR_MASK		GENMASK(6, 5)

#define BMA400_ACC_CONFIG1_REG		0x1a
#define BMA400_ACC_CONFIG1_ODR_MASK		GENMASK(3, 0)
#define BMA400_ACC_CONFIG1_ODR_MIN_RAW		0x05
#define BMA400_ACC_CONFIG1_ODR_LP_RAW		0x06
#define BMA400_ACC_CONFIG1_ODR_MAX_RAW		0x0b
#define BMA400_ACC_CONFIG1_ODR_MAX_HZ		800
#define BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ	25
#define BMA400_ACC_CONFIG1_ODR_MIN_HZ		12
#define BMA400_ACC_CONFIG1_NP_OSR_MASK		GENMASK(5, 4)
#define BMA400_ACC_CONFIG1_ACC_RANGE_MASK	GENMASK(7, 6)

#define BMA400_ACC_CONFIG2_REG      0x1b

/* Interrupt registers */
#define BMA400_INT_CONFIG0_REG	    0x1f
#define BMA400_INT_CONFIG0_GEN1_MASK		BIT(2)
#define BMA400_INT_CONFIG0_GEN2_MASK		BIT(3)
#define BMA400_INT_CONFIG0_DRDY_MASK		BIT(7)

enum bma400_generic_intr {

Annotation

Implementation Notes