drivers/iio/accel/kionix-kx022a.c
Source file repositories/reference/linux-study-clean/drivers/iio/accel/kionix-kx022a.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/accel/kionix-kx022a.c- Extension
.c- Size
- 38612 bytes
- Lines
- 1457
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/array_size.hlinux/bitmap.hlinux/cleanup.hlinux/delay.hlinux/device.hlinux/errno.hlinux/export.hlinux/interrupt.hlinux/math64.hlinux/minmax.hlinux/module.hlinux/mutex.hlinux/property.hlinux/regmap.hlinux/regulator/consumer.hlinux/slab.hlinux/string_choices.hlinux/sysfs.hlinux/time64.hlinux/types.hlinux/units.hlinux/iio/iio.hlinux/iio/buffer.hlinux/iio/sysfs.hlinux/iio/trigger.hlinux/iio/trigger_consumer.hlinux/iio/triggered_buffer.hasm/byteorder.hkionix-kx022a.h
Detected Declarations
struct kx022a_datafunction kx022a_get_mount_matrixfunction kx022a_read_availfunction kx022a_reg2freqfunction kx022a_reg2scalefunction __kx022a_turn_on_offfunction kx022a_turn_off_lockfunction kx022a_turn_on_unlockfunction kx022a_write_raw_get_fmtfunction __kx022a_write_rawfunction kx022a_write_rawfunction kx022a_fifo_set_wmifunction kx022a_get_axisfunction kx022a_read_rawfunction kx022a_set_watermarkfunction hwfifo_enabled_showfunction hwfifo_watermark_showfunction kx022a_drop_fifo_contentsfunction kx022a_get_fifo_bytes_availablefunction kx132_get_fifo_bytes_availablefunction __kx022a_fifo_flushfunction kx022a_fifo_flushfunction kx022a_set_drdy_irqfunction kx022a_prepare_irq_pinfunction kx022a_fifo_disablefunction kx022a_buffer_predisablefunction kx022a_fifo_enablefunction kx022a_buffer_postenablefunction kx022a_trigger_handlerfunction kx022a_irq_handlerfunction kx022a_irq_thread_handlerfunction kx022a_trigger_set_statefunction kx022a_chip_initfunction kx022a_probe_internal
Annotated Snippet
struct kx022a_data {
struct regmap *regmap;
const struct kx022a_chip_info *chip_info;
struct iio_trigger *trig;
struct device *dev;
struct iio_mount_matrix orientation;
int64_t timestamp, old_timestamp;
int irq;
int inc_reg;
int ien_reg;
unsigned int state;
unsigned int odr_ns;
bool trigger_enabled;
/*
* Prevent toggling the sensor stby/active state (PC1 bit) in the
* middle of a configuration, or when the fifo is enabled. Also,
* protect the data stored/retrieved from this structure from
* concurrent accesses.
*/
struct mutex mutex;
u8 watermark;
__le16 *fifo_buffer;
/* 3 x 16bit accel data + timestamp */
__le16 buffer[8] __aligned(IIO_DMA_MINALIGN);
struct {
__le16 channels[3];
aligned_s64 ts;
} scan;
};
static const struct iio_mount_matrix *
kx022a_get_mount_matrix(const struct iio_dev *idev,
const struct iio_chan_spec *chan)
{
struct kx022a_data *data = iio_priv(idev);
return &data->orientation;
}
enum {
AXIS_X,
AXIS_Y,
AXIS_Z,
AXIS_MAX
};
static const unsigned long kx022a_scan_masks[] = {
BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0
};
static const struct iio_chan_spec_ext_info kx022a_ext_info[] = {
IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kx022a_get_mount_matrix),
{ }
};
#define KX022A_ACCEL_CHAN(axis, reg, index) \
{ \
.type = IIO_ACCEL, \
.modified = 1, \
.channel2 = IIO_MOD_##axis, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_shared_by_type_available = \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.ext_info = kx022a_ext_info, \
.address = reg, \
.scan_index = index, \
.scan_type = { \
.sign = 's', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_LE, \
}, \
}
static const struct iio_chan_spec kx022a_channels[] = {
KX022A_ACCEL_CHAN(X, KX022A_REG_XOUT_L, 0),
KX022A_ACCEL_CHAN(Y, KX022A_REG_YOUT_L, 1),
KX022A_ACCEL_CHAN(Z, KX022A_REG_ZOUT_L, 2),
IIO_CHAN_SOFT_TIMESTAMP(3),
};
static const struct iio_chan_spec kx132_channels[] = {
Annotation
- Immediate include surface: `linux/array_size.h`, `linux/bitmap.h`, `linux/cleanup.h`, `linux/delay.h`, `linux/device.h`, `linux/errno.h`, `linux/export.h`, `linux/interrupt.h`.
- Detected declarations: `struct kx022a_data`, `function kx022a_get_mount_matrix`, `function kx022a_read_avail`, `function kx022a_reg2freq`, `function kx022a_reg2scale`, `function __kx022a_turn_on_off`, `function kx022a_turn_off_lock`, `function kx022a_turn_on_unlock`, `function kx022a_write_raw_get_fmt`, `function __kx022a_write_raw`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.