drivers/iio/accel/mma8452.c
Source file repositories/reference/linux-study-clean/drivers/iio/accel/mma8452.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/accel/mma8452.c- Extension
.c- Size
- 48637 bytes
- Lines
- 1849
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/mod_devicetable.hlinux/property.hlinux/i2c.hlinux/iio/iio.hlinux/iio/sysfs.hlinux/iio/buffer.hlinux/iio/trigger.hlinux/iio/trigger_consumer.hlinux/iio/triggered_buffer.hlinux/iio/events.hlinux/delay.hlinux/pm_runtime.hlinux/regulator/consumer.hlinux/types.h
Detected Declarations
struct mma8452_datastruct mma8452_event_regsstruct mma_chip_infofunction mma8452_drdyfunction mma8452_set_runtime_pm_statefunction mma8452_readfunction mma8452_show_int_plus_microsfunction mma8452_get_int_plus_micros_indexfunction mma8452_get_odr_indexfunction mma8452_get_power_modefunction mma8452_show_samp_freq_availfunction mma8452_show_scale_availfunction mma8452_show_hp_cutoff_availfunction mma8452_show_os_ratio_availfunction mma8452_get_samp_freq_indexfunction mma8452_get_scale_indexfunction mma8452_get_hp_filter_indexfunction mma8452_read_hp_filterfunction mma8452_read_rawfunction mma8452_calculate_sleepfunction mma8452_standbyfunction mma8452_activefunction mma8452_is_activefunction mma8452_change_configfunction mma8452_set_power_modefunction mma8452_freefall_mode_enabledfunction mma8452_set_freefall_modefunction mma8452_set_hp_filter_frequencyfunction __mma8452_write_rawfunction mma8452_write_rawfunction mma8452_get_event_regsfunction mma8452_read_event_valuefunction mma8452_write_event_valuefunction mma8452_read_event_configfunction mma8452_write_event_configfunction mma8452_transient_interruptfunction mma8452_interruptfunction mma8452_trigger_handlerfunction mma8452_reg_access_dbgfunction mma8452_get_mount_matrixfunction BITfunction mma8452_data_rdy_trigger_set_statefunction mma8452_trigger_setupfunction mma8452_trigger_cleanupfunction mma8452_resetfunction mma8452_probefunction mma8452_removefunction mma8452_runtime_suspend
Annotated Snippet
struct mma8452_data {
struct i2c_client *client;
struct mutex lock;
struct iio_mount_matrix orientation;
u8 ctrl_reg1;
u8 data_cfg;
const struct mma_chip_info *chip_info;
int sleep_val;
struct regulator *vdd_reg;
struct regulator *vddio_reg;
/* Ensure correct alignment of time stamp when present */
struct {
__be16 channels[3];
aligned_s64 ts;
} buffer;
};
/**
* struct mma8452_event_regs - chip specific data related to events
* @ev_cfg: event config register address
* @ev_cfg_ele: latch bit in event config register
* @ev_cfg_chan_shift: number of the bit to enable events in X
* direction; in event config register
* @ev_src: event source register address
* @ev_ths: event threshold register address
* @ev_ths_mask: mask for the threshold value
* @ev_count: event count (period) register address
*
* Since not all chips supported by the driver support comparing high pass
* filtered data for events (interrupts), different interrupt sources are
* used for different chips and the relevant registers are included here.
*/
struct mma8452_event_regs {
u8 ev_cfg;
u8 ev_cfg_ele;
u8 ev_cfg_chan_shift;
u8 ev_src;
u8 ev_ths;
u8 ev_ths_mask;
u8 ev_count;
};
static const struct mma8452_event_regs ff_mt_ev_regs = {
.ev_cfg = MMA8452_FF_MT_CFG,
.ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
.ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
.ev_src = MMA8452_FF_MT_SRC,
.ev_ths = MMA8452_FF_MT_THS,
.ev_ths_mask = MMA8452_FF_MT_THS_MASK,
.ev_count = MMA8452_FF_MT_COUNT
};
static const struct mma8452_event_regs trans_ev_regs = {
.ev_cfg = MMA8452_TRANSIENT_CFG,
.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
.ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
.ev_src = MMA8452_TRANSIENT_SRC,
.ev_ths = MMA8452_TRANSIENT_THS,
.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
.ev_count = MMA8452_TRANSIENT_COUNT,
};
/**
* struct mma_chip_info - chip specific data
* @name: part number of device reported via 'name' attr
* @chip_id: WHO_AM_I register's value
* @channels: struct iio_chan_spec matching the device's
* capabilities
* @num_channels: number of channels
* @mma_scales: scale factors for converting register values
* to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
* per mode: m/s^2 and micro m/s^2
* @all_events: all events supported by this chip
* @enabled_events: event flags enabled and handled by this driver
*/
struct mma_chip_info {
const char *name;
u8 chip_id;
const struct iio_chan_spec *channels;
int num_channels;
const int mma_scales[3][2];
int all_events;
int enabled_events;
};
enum {
idx_x,
idx_y,
idx_z,
Annotation
- Immediate include surface: `linux/module.h`, `linux/mod_devicetable.h`, `linux/property.h`, `linux/i2c.h`, `linux/iio/iio.h`, `linux/iio/sysfs.h`, `linux/iio/buffer.h`, `linux/iio/trigger.h`.
- Detected declarations: `struct mma8452_data`, `struct mma8452_event_regs`, `struct mma_chip_info`, `function mma8452_drdy`, `function mma8452_set_runtime_pm_state`, `function mma8452_read`, `function mma8452_show_int_plus_micros`, `function mma8452_get_int_plus_micros_index`, `function mma8452_get_odr_index`, `function mma8452_get_power_mode`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.