drivers/iio/accel/mxc4005.c
Source file repositories/reference/linux-study-clean/drivers/iio/accel/mxc4005.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/iio/accel/mxc4005.c- Extension
.c- Size
- 14233 bytes
- Lines
- 605
- Domain
- Driver Families
- Bucket
- drivers/iio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/module.hlinux/i2c.hlinux/iio/iio.hlinux/mod_devicetable.hlinux/regmap.hlinux/types.hlinux/iio/sysfs.hlinux/iio/trigger.hlinux/iio/buffer.hlinux/iio/triggered_buffer.hlinux/iio/trigger_consumer.h
Detected Declarations
struct mxc4005_dataenum mxc4005_axisenum mxc4005_rangefunction mxc4005_is_readable_regfunction mxc4005_is_writeable_regfunction mxc4005_read_xyzfunction mxc4005_read_axisfunction mxc4005_read_scalefunction mxc4005_set_scalefunction mxc4005_read_rawfunction mxc4005_write_rawfunction mxc4005_get_mount_matrixfunction mxc4005_trigger_handlerfunction mxc4005_clr_intrfunction mxc4005_set_trigger_statefunction mxc4005_trigger_reenfunction mxc4005_chip_initfunction mxc4005_probefunction mxc4005_suspendfunction mxc4005_resume
Annotated Snippet
struct mxc4005_data {
struct device *dev;
struct mutex mutex;
struct regmap *regmap;
struct iio_trigger *dready_trig;
struct iio_mount_matrix orientation;
/* Ensure timestamp is naturally aligned */
struct {
__be16 chans[3];
aligned_s64 timestamp;
} scan;
bool trigger_enabled;
unsigned int control;
unsigned int int_mask1;
};
/*
* MXC4005 can operate in the following ranges:
* +/- 2G, 4G, 8G (the default +/-2G)
*
* (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
* (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
* (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
*/
static const struct {
u8 range;
int scale;
} mxc4005_scale_table[] = {
{MXC4005_RANGE_2G, 9582},
{MXC4005_RANGE_4G, 19164},
{MXC4005_RANGE_8G, 38329},
};
static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
static struct attribute *mxc4005_attributes[] = {
&iio_const_attr_in_accel_scale_available.dev_attr.attr,
NULL,
};
static const struct attribute_group mxc4005_attrs_group = {
.attrs = mxc4005_attributes,
};
static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MXC4005_REG_XOUT_UPPER:
case MXC4005_REG_XOUT_LOWER:
case MXC4005_REG_YOUT_UPPER:
case MXC4005_REG_YOUT_LOWER:
case MXC4005_REG_ZOUT_UPPER:
case MXC4005_REG_ZOUT_LOWER:
case MXC4005_REG_DEVICE_ID:
case MXC4005_REG_CONTROL:
return true;
default:
return false;
}
}
static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MXC4005_REG_INT_CLR0:
case MXC4005_REG_INT_CLR1:
case MXC4005_REG_INT_MASK0:
case MXC4005_REG_INT_MASK1:
case MXC4005_REG_CONTROL:
return true;
default:
return false;
}
}
static const struct regmap_config mxc4005_regmap_config = {
.name = "mxc4005_regmap",
.reg_bits = 8,
.val_bits = 8,
.max_register = MXC4005_REG_DEVICE_ID,
.readable_reg = mxc4005_is_readable_reg,
.writeable_reg = mxc4005_is_writeable_reg,
};
static int mxc4005_read_xyz(struct mxc4005_data *data)
{
Annotation
- Immediate include surface: `linux/delay.h`, `linux/module.h`, `linux/i2c.h`, `linux/iio/iio.h`, `linux/mod_devicetable.h`, `linux/regmap.h`, `linux/types.h`, `linux/iio/sysfs.h`.
- Detected declarations: `struct mxc4005_data`, `enum mxc4005_axis`, `enum mxc4005_range`, `function mxc4005_is_readable_reg`, `function mxc4005_is_writeable_reg`, `function mxc4005_read_xyz`, `function mxc4005_read_axis`, `function mxc4005_read_scale`, `function mxc4005_set_scale`, `function mxc4005_read_raw`.
- Atlas domain: Driver Families / drivers/iio.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.