drivers/iio/adc/ad4130.c

Source file repositories/reference/linux-study-clean/drivers/iio/adc/ad4130.c

File Facts

System
Linux kernel
Corpus path
drivers/iio/adc/ad4130.c
Extension
.c
Size
55358 bytes
Lines
2124
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ad4130_setup_info {
	unsigned int			iout0_val;
	unsigned int			iout1_val;
	unsigned int			burnout;
	unsigned int			pga;
	unsigned int			fs;
	u32				ref_sel;
	enum ad4130_filter_type		filter_type;
	bool				ref_bufp;
	bool				ref_bufm;
};

struct ad4130_slot_info {
	struct ad4130_setup_info	setup;
	unsigned int			enabled_channels;
	unsigned int			channels;
};

struct ad4130_chan_info {
	struct ad4130_setup_info	setup;
	u32				iout0;
	u32				iout1;
	int				slot;
	bool				enabled;
	bool				initialized;
};

struct ad4130_filter_config {
	enum ad4130_filter_type		filter_type;
	unsigned int			odr_div;
	unsigned int			fs_max;
	enum iio_available_type		samp_freq_avail_type;
	int				samp_freq_avail_len;
	int				samp_freq_avail[3][2];
};

struct ad4130_state {
	struct regmap			*regmap;
	struct spi_device		*spi;
	struct clk			*mclk;
	struct regulator_bulk_data	regulators[4];
	u32				irq_trigger;
	u32				inv_irq_trigger;

	/*
	 * Synchronize access to members the of driver state, and ensure
	 * atomicity of consecutive regmap operations.
	 */
	struct mutex			lock;
	struct completion		completion;

	struct iio_chan_spec		chans[AD4130_MAX_CHANNELS];
	struct ad4130_chan_info		chans_info[AD4130_MAX_CHANNELS];
	struct ad4130_slot_info		slots_info[AD4130_MAX_SETUPS];
	enum ad4130_pin_function	pins_fn[AD4130_MAX_ANALOG_PINS];
	u32				vbias_pins[AD4130_MAX_ANALOG_PINS];
	u32				num_vbias_pins;
	int				scale_tbls[AD4130_REF_SEL_MAX][AD4130_MAX_PGA][2];
	struct gpio_chip		gc;
	struct clk_hw			int_clk_hw;

	u32			int_pin_sel;
	u32			int_ref_uv;
	u32			mclk_sel;
	bool			int_ref_en;
	bool			bipolar;

	unsigned int		num_enabled_channels;
	unsigned int		effective_watermark;
	unsigned int		watermark;

	struct spi_message	fifo_msg;
	struct spi_transfer	fifo_xfer[2];

	/*
	 * DMA (thus cache coherency maintenance) requires any transfer
	 * buffers to live in their own cache lines. As the use of these
	 * buffers is synchronous, all of the buffers used for DMA in this
	 * driver may share a cache line.
	 */
	u8			reset_buf[AD4130_RESET_BUF_SIZE] __aligned(IIO_DMA_MINALIGN);
	u8			reg_write_tx_buf[4];
	u8			reg_read_tx_buf[1];
	u8			reg_read_rx_buf[3];
	u8			fifo_tx_buf[2];
	u8			fifo_rx_buf[AD4130_FIFO_SIZE *
					    AD4130_FIFO_MAX_SAMPLE_SIZE];
};

static const char * const ad4130_int_pin_names[] = {

Annotation

Implementation Notes