drivers/iio/adc/ad4170-4.c

Source file repositories/reference/linux-study-clean/drivers/iio/adc/ad4170-4.c

File Facts

System
Linux kernel
Corpus path
drivers/iio/adc/ad4170-4.c
Extension
.c
Size
88412 bytes
Lines
3028
Domain
Driver Families
Bucket
drivers/iio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ad4170_chip_info {
	const char *name;
};

static const struct ad4170_chip_info ad4170_chip_info = {
	.name = "ad4170-4",
};

static const struct ad4170_chip_info ad4190_chip_info = {
	.name = "ad4190-4",
};

static const struct ad4170_chip_info ad4195_chip_info = {
	.name = "ad4195-4",
};

/*
 * There are 8 of each MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN
 * configuration registers. That is, there are 8 miscellaneous registers, MISC0
 * to MISC7. Each MISC register is associated with a setup; MISCN is associated
 * with setup number N. The other 5 above mentioned types of registers have
 * analogous structure. A setup is a set of those registers. For example,
 * setup 1 comprises of MISC1, AFE1, FILTER1, FILTER_FS1, OFFSET1, and GAIN1
 * registers. Also, there are 16 CHANNEL_SETUP registers (CHANNEL_SETUP0 to
 * CHANNEL_SETUP15). Each channel setup is associated with one of the 8 possible
 * setups. Thus, AD4170 can support up to 16 channels but, since there are only
 * 8 available setups, channels must share settings if more than 8 channels are
 * configured.
 *
 * If this struct is modified, ad4170_setup_eq() will probably need to be
 * updated too.
 */
struct ad4170_setup {
	u16 misc;
	u16 afe;
	u16 filter;
	u16 filter_fs;
	u32 offset; /* For calibration purposes */
	u32 gain; /* For calibration purposes */
};

struct ad4170_setup_info {
	struct ad4170_setup setup;
	unsigned int enabled_channels;
	unsigned int channels;
};

struct ad4170_chan_info {
	unsigned int input_range_uv;
	unsigned int setup_num; /* Index to access state setup_infos array */
	struct ad4170_setup setup; /* cached setup */
	int offset_tbl[10];
	u32 scale_tbl[10][2];
	bool initialized;
	bool enabled;
};

static const char * const ad4170_filt_names[] = {
	[AD4170_SINC5_AVG] = "sinc5+avg",
	[AD4170_SINC5] = "sinc5",
	[AD4170_SINC3] = "sinc3",
};

struct ad4170_state {
	struct mutex lock; /* Protect read-modify-write and multi write sequences */
	int vrefs_uv[AD4170_MAX_SUP];
	u32 mclk_hz;
	struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS];
	struct ad4170_chan_info chan_infos[AD4170_MAX_ADC_CHANNELS];
	struct completion completion;
	struct iio_chan_spec chans[AD4170_MAX_IIO_CHANNELS];
	struct spi_device *spi;
	struct regmap *regmap;
	int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
	__be32 bounce_buffer[AD4170_MAX_ADC_CHANNELS];
	struct spi_message msg;
	struct spi_transfer xfer;
	struct iio_trigger *trig;
	struct clk_hw int_clk_hw;
	unsigned int clock_ctrl;
	unsigned int pins_fn[AD4170_NUM_ANALOG_PINS];
	int gpio_fn[AD4170_NUM_GPIO_PINS];
	unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC];
	struct gpio_chip gpiochip;
	/*
	 * DMA (thus cache coherency maintenance) requires the transfer buffers
	 * to live in their own cache lines.
	 */
	u8 rx_buf[4] __aligned(IIO_DMA_MINALIGN);
};

Annotation

Implementation Notes